Rtl Tools & Methodology Engineer Job at AMD (San Jose)

Power Methodology Engineer, Data Center Hardware IPs

A senior power lead for power architecture solutions, specializing in areas like...

Location

United States , Santa Clara

Salary:

191040.00 - 286560.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Extensive industry experience, with a specialization in low-power-processor architectures or power management
Expertise in ASIC/SoC power analysis and optimization techniques
Working experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design)
AI/ML Concepts: Familiarity with machine learning algorithms and their application to power simulation/optimization, as well as an understanding of NPU function and AI workload characteristics
Proficiency in hardware description languages like Verilog or VHDL, and scripting
Strong analytical skills and experience with power analysis tools (e.g., PowerArtist, PTPX)
Expertise in hardware description languages (Verilog, VHDL), scripting (Python), and simulation/analysis tools
Strong analytical and problem-solving skills to tackle complex, multidisciplinary power and performance challenges
Several years of experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design)
Strong scripting and automation skills, preferably in Python

Job Responsibility

Focuses on optimizing the energy efficiency and power delivery of high-performance computing hardware used in large-scale AI and machine learning applications
Driving power methodology for AI-specific hardware components (like tensor cores and matrix multiplication engines) and using simulation tools (e.g., PowerArtist, PTPX) to estimate and optimize power consumption
Workload Optimization: Analyze the power and performance characteristics of AI, Graphics, Battery life WLs, especially specific WLs for NPUs, GPUs, and CPUs
Performance/Watt Optimization: Focus on maximizing performance while staying within strict power and thermal limits, which is critical for both data center and gaming applications
Power Optimization: Estimate and analyze power consumption at various stages of chip design (architecture, RTL, physical design)
Analysis and modeling: Creating power models and scripts for performance/power trade-offs
Methodology Development: Researching, developing, and deploying methodologies and automated flows (using scripting languages like Python or Perl) to enhance power analysis efficiency
Collaboration: Working with other teams, including RTL, Architecture, Physical Design, Emulation, software, Firmware to ensure power requirements are met across the hardware-software stack
Leadership: Mentoring junior team members and providing technical leadership on complex projects

Fulltime

New

Senior RTL Design Engineer

This is a hybrid role with four days per week at Cisco’s Yerevan office. Join th...

Location

Armenia , Yerevan

Salary:

Not provided

Duo Security

Expiration Date

Until further notice

Requirements

6+ years of industry experience in ASIC digital design
Proficient in Verilog/System Verilog coding
Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification)
Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories
Ability to write scripts using Python, Tcl, Make

Job Responsibility

Taking part in all aspects of digital design, from micro-architecture to RTL design and qualification
Sub-system/SoC integration and verification
Review/enhancement of RTL codes
Improve flows and methodologies to streamline IP/SoC development and integration
Work closely with the verification team for complex debugs to resolve verification failures
Close interaction with the physical design team to reach better physical design QoR

Fulltime

New

Senior RTL Design Engineer

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platf...

Location

Armenia , Yerevan

Salary:

Not provided

Cisco

Expiration Date

Until further notice

Requirements

5+ years of industry experience in ASIC digital design
Proficient in Verilog/System Verilog coding
Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification)
Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories
Ability to write scripts using Python, Tcl, Make
Good communications skills, self-motivated and well-organized

Job Responsibility

You will be a key member of the Silicon One development organization, collaborating closely with Front-end RTL and backend physical design teams to gain a deep understanding of chip architecture
Your primary focus will be to drive high-quality Design for Test (DFT) verification, ensuring robust and reliable silicon solutions that meet Cisco’s standards for performance and innovation
Taking part in all aspects of digital design, from micro-architecture to RTL design and qualification
Sub-system/SoC integration and verification
Review/enhancement of RTL codes
Improve flows and methodologies to streamline IP/SoC development and integration
Work closely with the verification team for complex debugs to resolve verification failures
Close interaction with physical design team to reach better physical design QoR

Fulltime

RTL Emulation Engineer

As a member of the Serdes Technologies Group, you will help bring to life cuttin...

Location

United States , San Jose

Salary:

191040.00 - 286560.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
Experience with various Emulation systems
Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Build flows for emulation platforms that are representive of the Si Design
Test coverage and test cost reduction analysis
Post silicon support to ensure successful bring up and enhance yield learning

Fulltime

Rtl Design Engineer

This exciting position in AMD's Silicon IP solutions & SOC group will provide th...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

A minimum of 8 years of experience is required
Proven experience in Silicon IP development process, methodologies, Design for Test methodologies
Experience with Verilog RTL design, VCS simulation tool, Perl/Shell scripting
Proven experience in contributing to complex silicon tapeouts
Detailed understanding and proven track record of developing any of the leading edge PCIe, Full featured DMAs, NVMe based Storage IP, networking IP solutions such as Ethernet, TCP/IP, RDMA IPs
Strong oral and written communication skills are essential
The ideal candidate will be a proactive contributor to the RTL design methodologies
Ability to work on complex issues where analysis situations or data requires an in-depth evaluation of variable factors
To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups
A Bachelor of Science Degree in Electrical Engineering or Computer Science, a master’s degree or equivalent experience is required

Job Responsibility

Define u-architecture from the architecture definition
Evaluating and executing design and development plans for IPs
RTL design, IP Integration & documentation
Participating in and acting as a senior technical reviewer for various u-architecture and implementation reviews within the development organization
Working with stakeholders to develop comprehensive testing plans including Compliance and Interop testing
Critically Review and provide feedback on the Design Implementations and Verification plans
Acting as technical mentor to junior engineers

RTL & Codesign Engineer

OpenAI’s Hardware organization develops silicon and system-level solutions desig...

Location

United States , San Francisco

Salary:

225000.00 - 445000.00 USD / Year

OpenAI

Expiration Date

Until further notice

Requirements

Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization
Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out
Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems
Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies
Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams
Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits
Passion for building industry-leading massive-scale hardware systems
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

Job Responsibility

Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems
Contribute to architectural studies including performance modeling and feasibility analysis
Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit
Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration
Build and review performance and functional models to validate design intent
Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle

What we offer

Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
401(k) retirement plan with employer match
Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
Mental health and wellness support
Employer-paid basic life and disability coverage
Annual learning and development stipend to fuel your professional growth
Daily meals in our offices, and meal delivery credits as eligible

Fulltime

RTL Design Engineer

Our client is a game-changer start-up that is designing and building the simulat...

Location

United States , San Francisco

Salary:

180000.00 - 250000.00 USD / Year

80Twenty

Expiration Date

Until further notice

Requirements

5+ years in RTL design or DV
Strong background in verification methodologies (UVM, SystemVerilog, testbench development)
Experience with synthesis, timing analysis, and debugging tools
Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor Graphics)
Strong communication skills for cross-functional collaboration for researchers who are not hardware experts

Job Responsibility

Lead the building of the hardest technical challenges in hardware design: Design challenges across RTL generation, verification, debugging, timing closure, specification alignment
Create RTL design and verification problems that mirror industry complexity and build realistic RTL codebases
QA environments and manage overseas hardware teams
Work directly with lab AI researchers to understand agent capabilities and training requirements
Have direct input on which hardware workflows we tackle next. You will decide which design or verification tasks are the highest-value targets for AI automation

What we offer

Paid relocation and sponsorship
Generous equity compensation

Fulltime

ASIC RTL Design Engineer

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate, implement, and verify RTL code for complex ASICs
Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Lead design reviews and provide mentorship to junior engineers
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

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Rtl Tools & Methodology Engineer

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