Rtl Tools & Methodology Engineer Job at AMD (San Jose)

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly skilled and experienced Principal Engineer to join our A...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field
8+ years of experience in ASIC development, with a proven track record of leading complex project
Hands on in IP / blocks / subsystem complex design in verilog / sysverilog
Strong digital design development and execution skills , solving bugs
Experience in grooming team of 1-4 engineers, interacting with many team
Deep expirience in debug , solving problem, see the architecture view, proposing solutions.
Hands-on experience with industry-standard EDA tools and design flows
Deep knowledge on PCIe, axi , DMA, AHB interfaces
Expertise in high-performance and low-power design techniques
Excellent communication skills, both verbal and written, with the ability to articulate complex technical concepts clearly

Job Responsibility

Design and implements IPs and subsystems
Dealing the best of class IPs for all SanDisk products

Fulltime

Power Methodology Engineer, Data Center Hardware IPs

A senior power lead for power architecture solutions, specializing in areas like...

Location

United States , Santa Clara

Salary:

191040.00 - 286560.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Extensive industry experience, with a specialization in low-power-processor architectures or power management
Expertise in ASIC/SoC power analysis and optimization techniques
Working experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design)
AI/ML Concepts: Familiarity with machine learning algorithms and their application to power simulation/optimization, as well as an understanding of NPU function and AI workload characteristics
Proficiency in hardware description languages like Verilog or VHDL, and scripting
Strong analytical skills and experience with power analysis tools (e.g., PowerArtist, PTPX)
Expertise in hardware description languages (Verilog, VHDL), scripting (Python), and simulation/analysis tools
Strong analytical and problem-solving skills to tackle complex, multidisciplinary power and performance challenges
Several years of experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design)
Strong scripting and automation skills, preferably in Python

Job Responsibility

Focuses on optimizing the energy efficiency and power delivery of high-performance computing hardware used in large-scale AI and machine learning applications
Driving power methodology for AI-specific hardware components (like tensor cores and matrix multiplication engines) and using simulation tools (e.g., PowerArtist, PTPX) to estimate and optimize power consumption
Workload Optimization: Analyze the power and performance characteristics of AI, Graphics, Battery life WLs, especially specific WLs for NPUs, GPUs, and CPUs
Performance/Watt Optimization: Focus on maximizing performance while staying within strict power and thermal limits, which is critical for both data center and gaming applications
Power Optimization: Estimate and analyze power consumption at various stages of chip design (architecture, RTL, physical design)
Analysis and modeling: Creating power models and scripts for performance/power trade-offs
Methodology Development: Researching, developing, and deploying methodologies and automated flows (using scripting languages like Python or Perl) to enhance power analysis efficiency
Collaboration: Working with other teams, including RTL, Architecture, Physical Design, Emulation, software, Firmware to ensure power requirements are met across the hardware-software stack
Leadership: Mentoring junior team members and providing technical leadership on complex projects

Fulltime

RTL Design Engineer

Our client is a game-changer start-up that is designing and building the simulat...

Location

United States , San Francisco

Salary:

180000.00 - 250000.00 USD / Year

80Twenty

Expiration Date

Until further notice

Requirements

5+ years in RTL design or DV
Strong background in verification methodologies (UVM, SystemVerilog, testbench development)
Experience with synthesis, timing analysis, and debugging tools
Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor Graphics)
Strong communication skills for cross-functional collaboration for researchers who are not hardware experts

Job Responsibility

Lead the building of the hardest technical challenges in hardware design: Design challenges across RTL generation, verification, debugging, timing closure, specification alignment
Create RTL design and verification problems that mirror industry complexity and build realistic RTL codebases
QA environments and manage overseas hardware teams
Work directly with lab AI researchers to understand agent capabilities and training requirements
Have direct input on which hardware workflows we tackle next. You will decide which design or verification tasks are the highest-value targets for AI automation

What we offer

Paid relocation and sponsorship
Generous equity compensation

Fulltime

ASIC RTL Design Engineer

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate, implement, and verify RTL code for complex ASICs
Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Lead design reviews and provide mentorship to junior engineers
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Staff Engineer, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5-8 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate and develop RTL code for complex ASICs
Contribute in SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

ASIC Design Engineer

Join our dynamic ASIC design team at HPE Aruba Networking, where we’re building ...

Location

United States , Roseville

Salary:

130500.00 - 300000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or equivalent
6–10 years of experience in VLSI design, verification, or implementation
Deep understanding of digital logic, computer architecture, and VLSI fundamentals
Proficiency in RTL design (Verilog/SystemVerilog), scripting (Python/TCL), and EDA tools (Synopsys, Cadence, etc.)
Strong analytical and problem-solving skills
Excellent verbal and written communication skills
Experience working in cross-functional or global teams

Job Responsibility

Lead project teams of internal and outsourced engineers through all stages of VLSI design—from architecture and RTL to validation and physical implementation
Drive architecture and logic design decisions, ensuring alignment with performance, power, and area goals
Review and evaluate designs for compliance with internal standards and industry best practices
Collaborate across functions to integrate VLSI components into broader system platforms
Provide technical leadership and mentorship to junior engineers
Champion innovation by integrating new technologies and methodologies into our design flows
Contribute to the selection and development of future technical leaders

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Technologist, ASIC Development Engineering

We are looking for a highly skilled and experienced individual for SoC PD lead p...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field
A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs
Proven ability in technically leading a small/medium-sized team for executing projects preferred
Hands-on experience on the entire PD Flow from RTL to GDSII
Should have a good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains
Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc)
Exposure to static timing analysis fixes including automated ECO generation
Strong in areas on CTS, Power, Bump planning, Floorplan
Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies
Library preparation in any environment (Synopsys, Cadence, etc)

Job Responsibility

To be responsible for leading RTL-to-GDSII SoC implementation effort
To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc.
To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity
To ensure process compliance during project execution and enable / participate in technical discussions/reviews
To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations
Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team’s workflow
Foster a culture of innovation, collaboration, and continuous improvement

Fulltime

Rtl Design Engineer

This exciting position in AMD's Silicon IP solutions & SOC group will provide th...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

A minimum of 8 years of experience is required
Proven experience in Silicon IP development process, methodologies, Design for Test methodologies
Experience with Verilog RTL design, VCS simulation tool, Perl/Shell scripting
Proven experience in contributing to complex silicon tapeouts
Detailed understanding and proven track record of developing any of the leading edge PCIe, Full featured DMAs, NVMe based Storage IP, networking IP solutions such as Ethernet, TCP/IP, RDMA IPs
Strong oral and written communication skills are essential
The ideal candidate will be a proactive contributor to the RTL design methodologies
Ability to work on complex issues where analysis situations or data requires an in-depth evaluation of variable factors
To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups
A Bachelor of Science Degree in Electrical Engineering or Computer Science, a master’s degree or equivalent experience is required

Job Responsibility

Define u-architecture from the architecture definition
Evaluating and executing design and development plans for IPs
RTL design, IP Integration & documentation
Participating in and acting as a senior technical reviewer for various u-architecture and implementation reviews within the development organization
Working with stakeholders to develop comprehensive testing plans including Compliance and Interop testing
Critically Review and provide feedback on the Design Implementations and Verification plans
Acting as technical mentor to junior engineers

Rtl Tools & Methodology Engineer

AMD

Location:
United States , San Jose

Category:
IT - Software Development

Contract Type:
Employment contract

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
May 04, 2026

Looking for more opportunities? Search for other job offers that match your skills and interests.

Similar Jobs for Rtl Tools & Methodology Engineer

Principal Engineer, ASIC Development Engineering (RTL Design)