CrawlJobs Logo
AMD Logo AMD · IT - Software Development

Rtl Synthesis And Constraints Lead

India, Hyderabad · Job Posted May 04, 2026
Apply Position
Job Link Share

Job Description

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. Looking for strong RTL designer having 7-10 years of experience for timing constraint design and sign-off with Physical design team for an SOC subsystem. This role require strong digital design and SOC quality and constraint development for various for Processor and Interconnect based system design that also includes peripherals. The preference is for candidates who have delivered and worked for SOC design as Subsystem Timing constraint Lead and understands SOC constraints requirements. The selected person will own subsystem constraint development, debug and sign-off for SOCs in deep sub-micron technology.

Job Responsibility

  • Develop timing constraints for Subsystem for SOC
  • Work with RTL leads and use or define best practices for constraint development
  • Collaborate with Physical design and DFT constraints team members for timing sign-off
  • Ensure timely delivery of projects while meeting quality standards
  • Provide strong technical solution to internal and external stakeholders

Requirements

  • 7-10 years of experience
  • Proven experience in SOC timing lead role with focus on Timing closure of subsystem IP and delivery to SOC to PD teams
  • Expertise and strong understanding of RTL quality checks and constraints debug for Subsystem IP
  • Excellent communication skill
  • Strong analytical and problem-solving abilities, including designing experiments for performance
  • Self-motivated and proactive in driving initiatives
  • Bachelor's or Master's degree in Computer Engineering or Electrical Engineering
AMD - All Job Offers

Looking for more opportunities?

Search for other job offers that match your skills and interests.

Suggested Tags: Frontend Developer Secretary Talent Manager Salesforce Administrator Data Analyst
Similar Jobs for

Rtl Synthesis And Constraints Lead

8 matching positions

Rtl Design Lead - Ip Design

As a member of the Computing and Graphics Group, you will help bring to life cut...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 8-12 years full-time experience in IP hardware design
  • Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
  • Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
  • Clock domain crossing (CDC) tools
  • Detailed understanding of SoC design flows
  • Understanding of IP/SS/SoC Power Management techniques – Power Gating, Clock Gating
  • Experience with embedded processors and data fabric architectures (NoC)
  • Outstanding interaction skills while communicating both written and verbally
  • Ability to work with multi-level functional teams across various geographies
  • Outstanding problem-solving and analytical skills
Job Responsibility
Job Responsibility
  • Design of IP and subsystems with integration of AMD and other 3rd party IPs
  • Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs
  • Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC
  • Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up
What we offer
What we offer
  • AMD benefits at a glance
  • Fulltime
Read More
Arrow Right

Technologist, ASIC Development Engineering (RTL Design and SOC)

Are you ready to push the boundaries of what's possible in technology? Join the ...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
  • Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
  • Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
  • Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
  • Proficiency in scripting languages (e.g., Python, TCL) for automation
  • Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
  • Strong problem-solving skills and the ability to thrive in a dynamic environment
  • Excellent communication and teamwork abilities
Job Responsibility
Job Responsibility
  • Innovate, implement, and verify RTL code for complex ASICs
  • Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
  • Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
  • Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
  • Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
  • Lead design reviews and provide mentorship to junior engineers
  • Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
  • Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design
  • Fulltime
Read More
Arrow Right

Technologist, ASIC Development Engineering (RTL Design and SoC architecture, Lint)

Are you ready to push the boundaries of what's possible in technology? Join the ...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
  • Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
  • Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
  • Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
  • Proficiency in scripting languages (e.g., Python, TCL) for automation
  • Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
  • Strong problem-solving skills and the ability to thrive in a dynamic environment
  • Excellent communication and teamwork abilities
Job Responsibility
Job Responsibility
  • Innovate, implement, and verify RTL code for complex ASICs
  • Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
  • Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
  • Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
  • Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
  • Lead design reviews and provide mentorship to junior engineers
  • Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
  • Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design
  • Fulltime
Read More
Arrow Right

Asic Engineer, Physical Design

Meta is building custom silicon to power the next generation of infrastructure a...
Location
Location
United States , Sunnyvale, CA
Salary
Salary:
178000.00 - 250000.00 USD / Year
meta.com Logo
Meta
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of experience in ASIC physical design, including hands-on ownership of full physical implementation flows from floorplanning through tapeout
  • 8+ years of experience with industry-standard EDA tools for placement, routing, clock tree synthesis, and signoff (e.g., Synopsys IC Compiler, Cadence Innovus, Primetime, Calibre)
  • Experience with static timing analysis, timing constraint development, and multi-corner multi-mode closure at advanced process nodes (7nm or below)
  • Experience defining and improving physical design methodologies, flows, and automation scripts at an organizational level
  • Experience collaborating cross-functionally with RTL design, circuit design, and verification teams to resolve physical implementation challenges
Job Responsibility
Job Responsibility
  • Lead physical implementation of complex ASIC blocks or full chips, including floorplanning, placement, clock tree synthesis, routing, and signoff across advanced process nodes
  • Define and drive physical design methodology, flow development, and best practices across the physical design organization
  • Perform and own timing closure, including static timing analysis, timing constraint authoring, and multi-corner multi-mode signoff
  • Drive power integrity analysis and optimization, including IR drop, electromigration, and dynamic power reduction techniques
  • Collaborate with RTL design and architecture teams to provide physical design feedback on microarchitecture decisions, floorplan feasibility, and design-for-manufacturability
  • Partner with custom layout and circuit design teams to integrate analog and mixed-signal blocks into the digital physical implementation flow
  • Develop and maintain physical design scripts, automation flows, and runsets to improve team productivity and implementation quality
  • Conduct design rule check and layout versus schematic verification, resolving violations in coordination with foundry and design teams
  • Evaluate and qualify new EDA tools and process design kits, providing technical recommendations to improve physical implementation outcomes
  • Mentor other engineers on physical design techniques, flow improvements, and signoff methodology across the team
What we offer
What we offer
  • bonus
  • equity
  • benefits
  • Fulltime
Read More
Arrow Right

Sr Physical Design Engineer

This is an on-site, hybrid opportunity. This is not a remote work opportunity. E...
Location
Location
United States , Austin
Salary
Salary:
162000.00 - 243000.00 USD / Year
ericsson.com Logo
Ericsson
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 10+ years of physical design experience and minimum of a BS EE/CE
  • Expert in one or many of these areas – Methods to improve PPA, RTL checks and Synthesis, STA Constraints, DFT clocking architecture, Physical design of high speed interface IPs
  • Knowledge of System Verilog or VHDL
  • Accomplished at problem resolution and execution per project plan/needs
  • Prior experience in a Senior or Lead Engineer role, including direct responsibility for guiding and mentoring junior team members and setting technical direction
  • Highly team oriented
Job Responsibility
Job Responsibility
  • Be an empowered designer tasked with improving PPA of Ericsson ASICs
  • Evaluate feasibility of architectural features through back end implementation
  • Partner with front end design teams to address timing, power and congestion challenges
  • Deliver a synthesized netlist to ASIC BE vendor, and collaborate with vendor to address physical design tradeoffs
  • Work with DFT and architecture teams to develop timing constraints
  • Provide technical leadership and direction for junior members of the team
  • Participate in defining flows, methods and drive continuous improvement
What we offer
What we offer
  • Annual bonus
  • Choice of three medical plan options and a dental plan option
  • 401(k) Plan with automatic 3% company contribution and matching
  • Basic life insurance and basic accidental death and dismemberment coverage
  • Short-term and long-term disability coverage
  • Stock Purchase Plan
  • 15 days of accrued vacation per year
  • Up to 3 personal days per year
  • 11 annual holidays
  • 8 hours of volunteer time
  • Fulltime
Read More
Arrow Right

Quantum ASIC Project Lead

Microsoft's Quantum team is dedicated to developing the first scalable, fault-to...
Location
Location
United States , Redmond
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment
  • OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
  • OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Ability to leverage AI tools to drive innovation and efficiency
  • Ability to work in an 'AI-first' environment using modern AI tools
  • 15+ years of experience in digital design, including microarchitecture specification and RTL coding in Verilog and SystemVerilog
  • 8+ years of hands-on experience with synthesis, timing constraints, and Power/Performance/Area (PPA) trade-offs
  • 5+ years of experience leading SoC integration through successful ASIC tapeouts
Job Responsibility
Job Responsibility
  • Lead ASIC projects for Microsoft's quantum solutions, partnering with IP owners to develop IP blocks, integrating them at the SoC top level, and working with Digital Verification (DV), Synthesis, Design-For-Test (DFT), and Physical Design teams to prepare the SoC for tapeout
  • Own post-silicon test and scan, validation, device characterization, and the path to production
  • Coordinate the work of engineers, contractors, and contracting agencies delivering portions of the SoC
  • Drive microarchitecture and Register-Transfer-Level (RTL) design, coding, and verification of complex IP blocks, with an emphasis on meeting stringent power, performance, and timing goals
  • Develop constraints, power intent, synthesis, and static checks including LINT, Clock-Domain Crossing, and Reset-Domain Crossing
  • Build basic test benches and support verification, DFT, and post-silicon validation activities alongside verification and product teams
  • Collaborate effectively with architects, analog mixed-signal designers, verification engineers, physical design and DFT teams, and other front-end designers
  • Set up and manage databases and flows for SoC and IP repositories
  • Align development methodologies across teams and drive continuous improvement of RTL processes for at-scale execution
What we offer
What we offer
  • Certain roles may be eligible for benefits and other compensation
  • Fulltime
Read More
Arrow Right

Lead Soc Physical Design Engineer

As a member of the Strategic Silicon Solution Group Full Chip Physical Design te...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Minimum 15+ years of relevant work experience
  • Expertise in ICC2/FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools
  • Expertise in Signoff tools like Primetime for Timing, Calibre for DRC/LVS, Ansys Redhawk on EMIR, PT-PX for Power signoff
  • Should have worked as a go to person or technical lead for at least few full chip projects
  • Strong technical leadership and ability to mentor/guide/coach design engineers
  • Strong inter-personal skills and ability to collaborate with teams spread across multiple geos
  • Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts
  • Bachelors or Master's degree in Computer/Electronics/Electrical Engineering
  • Experience in 5nm & below technologies
  • Hands-on in reference flows, excellent debugging skills
Job Responsibility
Job Responsibility
  • Full chip level Die size estimation, Floor-planning, Power planning, IO planning, package compatibility, IO ring creation and ESD analysis
  • Full chip Hierarchical planning, block planning , block level constraints, hierarchical clock tree implementation, block integration and chip finishing
  • Low power design with power estimation/optimization including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption
  • Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPF
  • Full chip / sub-system level constraints, MMMC & cross talk aware timing closure with latest OCV based analysis
  • RTL2GDSII design implementation and flow debug top down or bottoms up at chip level
  • PPA (Power, Performance, Area and Schedule) closure and flow development for key IPs like CPU, Graphics, Multimedia, Fabric cores and/or other critical sub-systems
  • Low Power signoff like Static and Dynamic power analysis at top level and/or sub-system level
  • Full chip / sub system level Clock tree synthesis and advanced clock tree implementation
  • Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion and logic equivalence
Read More
Arrow Right

Principal Silicon Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Mountain View
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • Provide proof of country of citizenship or proof of US residency or other protected status for export control assessment
  • Bachelor of Science in Electrical or Computer Engineering
  • 8+ years of experience in RTL design and design checks (CDC/RDC/VCLP/LINT)
  • 8+ years of experience in Synthesis, Timing constraints and Power Performance Area (PPA) trade-offs
  • Proficiency in RTL to Physical Design collateral development including timing and synthesis constraints
  • Knowledge of full RTL2GDS flow
  • Hands-on experience with industry tools for synthesis, STA, and PD flows (e.g., PrimeTime, Genus/DC, Innovus/ICC2)
Job Responsibility
Job Responsibility
  • Serve as the middle-engineering technical leader at the intersection of RTL, physical design, and mixed-signal integration for Azure’s custom silicon programs
  • Ensure that design intent—digital and mixed-signal—is captured accurately in constraints, flows, and sign-off methodologies
  • Lead the capture and validation of design intent for digital and mixed-signal blocks, ensuring accurate constraints and seamless integration across front-end and physical design flows
  • Provide static timing leadership for mixed-signal interfaces, driving timing closure, exception quality, and correlation across corners
  • Partner closely with RTL, PD, mixed-signal, DFT, and CAD teams to resolve cross-domain issues and maintain alignment on timing, power, and functional requirements
  • Run, review and debug physical design flows, timing reports, ensuring consistency with synthesis and STA assumptions and driving convergence through targeted mitigations
  • Contribute to design automation including leveraging AI, constraint-checking, and flow improvements that enhance execution efficiency and PPA
  • Operate with limited direction, demonstrating strong ownership, attention to detail, and the ability to communicate clear, data-driven status, risks, and mitigation plans to program leadership
  • Fulltime
Read More
Arrow Right