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Rtl Intern

etched.com Logo

Etched

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Location:
United States , San Jose

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Category:
IT - Software Development

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Contract Type:
Not provided

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Salary:

Not provided
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Job Description:

As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block development, and participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced, high-autonomy environment.

Job Responsibility:

  • Help design microarchitecture and implement logic in verilog
  • Work with cutting-edge machine learning architectures
  • Contribute to RTL block development
  • Participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback

Requirements:

  • Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field
  • Familiarity with high-speed digital logic
  • Exposure to ASIC or SoC design concepts
  • Familiarity with SystemVerilog, UVM, or Python
  • Familiarity with verification work and writing test benches
  • Familiarity with physical design flows and tooling
  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Nice to have:

  • Familiarity with transformer models and machine learning
  • Familiarity with numerical representations and functions
  • Familiarity with clocking and reset schemes
  • Ability to program with Python or another scripting language
What we offer:
  • Generous housing support for those relocating
  • Daily lunch and dinner in our office
  • Direct mentorship from industry leaders and world-class engineers
  • Opportunity to work on one of the most important problems of our time

Additional Information:

Job Posted:
February 18, 2026

Employment Type:
Fulltime
Work Type:
On-site work
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