RTL Emulation Engineer Job at AMD (San Jose)

Emulation Engineer

As an Emulation Verification Engineer in AMD's Server SoC team, you'll be at the...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience in SystemVerilog, UVM, and emulation platforms
Proficiency in debugging tools and scripting languages like Python, Perl, or TCL
Familiarity with RTL design (Verilog/VHDL) and simulation tools
Solid understanding of SoC architecture, memory protocols, and interface standards
Familiarity with Gate level emulation in emulation platforms (e.g., Palladium, Veloce, Zebu)
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Bring-up and debug of large SoC designs on emulation platforms (e.g., Palladium, Veloce, Zebu)
Develop and execute test plans to validate functionality, performance, and power on emulators
Create and integrate monitors, checkers, and assertions in SystemVerilog/UVM environments
Collaborate with cross-functional teams including RTL design, architecture, firmware, and post-silicon validation
Analyze failures, root-cause bugs, and drive fixes in pre-silicon environments
Maintain and enhance emulation infrastructure and workflows

Fulltime

Staff Silicon Design Engineer - Emulation

A successful candidate will work with senior design and design verificaiton team...

Location

Serbia , Belgrade

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Experience in system and subsystem level designs
Experience with FPGA flows, synthesis and PnR
Experience in RTL design, verification, and embedded FW
Excellent programing skills in C/C++, SystemVerilog
Experience working with Verilog/SystemVerilog based designs
Experience with UVM based testbenches
Strong debugging and problem-solving skills
Debugging experience with waveform analyzers
Scripting/preprocessing
Experience working in emulation and prototyping

Job Responsibility

Execute emulation test plans, ensuring high-quality outcomes and adherence to timelines
Collaborate effectively with team members across North America to align on project goals, share insights, and implement best practices
Contribute in the design and implementation of emulation test benches
Contribute into continuously improving the emulation methodology
Experience implementing synthesizable models using SystemVerilog
Drive debug with designers and verifiers
Collaborate with IP design and verification teams on test planning and task execution
Work on various emulation methodologies such as: Transactors, Simulation Acceleration, Hybrid VMs
Execute verification of the latest features and protocols
Integrate, bring-up and debug standard interfaces like UART, JTAG, I2C, USB

Fulltime

Senior Emulation Engineer

We are looking for an adaptive, self-motivative design emulation engineer to joi...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Hands-on experience with Veloce and familiarity with ZeBu emulation flows
Strong C/C++ programming for transactors and host applications
Good understanding of PCIe, Ethernet, or RISC-V (SiFive) processors
Solid knowledge of Verilog/SystemVerilog RTL and verification flows
Strong Verilog/SystemVerilog skills to design shims, wrappers, and custom IP RTL for integration into emulation models
Minimum 5+ years of experience in emulation, verification, or related SoC development roles
Bachelors or Masters degree in Electrical/Electronics Engineering

Job Responsibility

Build and bring up emulation models (RTL cleanup, synthesis, compilation, partitioning)
Develop and integrate transactors/BFMs using C/C++, DPI, SCE-MI
Bring up PCIe and Ethernet interfaces in emulation (link training, enumeration, protocol debug)
Debug emulation failures using waves, logs, and hardware traces
Work closely with design/DV/software teams for SoC bring-up and test execution
Modify/extend verification testcases when required and execute them in simulation/emulation

Fulltime

Lead Platform Emulation Engineer

The focus of this role is to plan, build, execute the verification, validation/e...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Computer/Electronics/Electrical Engineering with 18+ years of experience
Experience with BIOS/OS bring up on full X86 SOC emulation platform
Proficient in IP level ASIC verification, experience working with CPU, GPU, and Memory subsystem
Proficient in debugging firmware and RTL code using simulation tools
Good understanding of PCIe/USB/Ethernet standards
safety concepts/IPs
Must have hands-on experience on Zebu/Palladium/Veloce platform to bring-up SOC
SOC design model build experience
Experienced with Verilog, System Verilog, C, and C++
Experience in writing and debugging testbenches

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Drive Emulation Methodologies, SOC Design Model and Test Architecture for full chip SOC and hybrid models
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed Pre-Silicon Emulation tests
Debug test failures to determine the root cause
work with RTL and firmware engineers to resolve design defects and correct any test or infra issues
Responsible for writing directed tests to verify features in a co-simulated and emulated/FPGA hardware environment
Responsible for writing monitors and checkers to support end-to-end firmware/hardware validation
Responsible for running emulator workloads to test new features and debug technical issues using logs, waveform dumps and RTL debug

Emulation Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great pro...

Location

United States , Austin

Salary:

121680.00 - 182520.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Experience with FPGA and/or emulation platforms (ZeBu, HAPs, Veloce)
Scripting with Perl or equivalent languages
Experience debugging failures using waveform viewers, log files, and microcode trace dumps
Knowledge of UEFI, core-boot, Linux, Windows Operating Systems
Knowledge of x86 and/or ARM SoC Architecture
Coding in x86 Assembly language
Strong knowledge of microprocessor architecture (x86 preferred)
Bachelors or Masters degree in EE, CE, or CS preferred

Job Responsibility

Come join the team responsible for driving AMD Core’s Shift-Left strategies
Interact with multiple stakeholders (firmware/BIOS, RTL designers, DV, system architects) to plan, create, execute, and debug core on emulators
Defining and implementing test plans including stimulus, checking and functional coverage plans
Developing test benches and test bench components in C++
Responsible for writing monitors and checkers to support end-to-end core emulation infrastructure
Debugging regression fails and fixing verification issues or working with designers to fix design bugs
Assist with silicon observations often requiring replication of behaviors in simulation to root cause
Responsible for running emulator workloads to test all new features
Create hardware emulation build to verify the IP functional performance
Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility

Fulltime

Staff/ Sr Staff RTL Design Engineer

Synopsys software engineers are key enablers in the world of Electronic Design A...

Location

India , Bengaluru

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

3-5 years of relevant experience in ASIC digital design and verification
Proficiency in RTL simulation, logic synthesis, and timing verification tools
Deep expertise in UVM, SystemVerilog, and protocol verification (e.g., IEEE1500, IEEE1687, AXI, AMBA)
Hands-on experience with VIPs and transactors in simulation and emulation environments
Strong understanding of DFT architectures, interconnects, and cache coherency protocols
Familiarity with debug tools such as Verdi and workflows for performance analysis
Programming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl
Experience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking

Job Responsibility

Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks
Performing digital design validation and functional verification at both block and SoC levels
Executing logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs
Applying DFT (Design-for-Test) expertise for comprehensive memory and logic testing
Identifying and troubleshooting design timing and DFT functional issues to optimize chip performance
Utilizing and scripting in languages such as Tcl to automate design and verification workflows
Defining architecture, logic, test bench designs, and embedded software functions for advanced test and analytics
Developing and maintaining technical collateral including test suites, protocol documentation, and debug guides
Collaborating with R&D and marketing teams to define new features, drive enhancements, and align product roadmaps
Delivering product training, managing customer support cases, and ensuring turnaround time (TAT) metrics are met or exceeded

What we offer

Comprehensive medical and healthcare plans that work for you and your family
In addition to company holidays, we have ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

SOC Verification Manager/Lead

We are seeking an experienced and highly motivated Verification experts to lead ...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

12–20 years of experience in VLSI Design Verification with a strong focus on SoC verification
Proven experience in SoC-Level Verification, SoC Verification Architecture, Power Management Verification, Low-Power Verification, Functional Verification and Coverage Closure
Strong understanding of SoC architectures involving CPUs, interconnects, memory subsystems, peripherals, and accelerators
Expertise in SystemVerilog and UVM-based verification methodologies
Hands-on experience with assertion-based verification (SVA)
Strong experience with UPF/CPF and power-aware simulation flows
Deep understanding of power domains, retention strategies, isolation techniques, level shifters, dynamic voltage and frequency scaling (DVFS), power state management
Experience with verification planning, coverage analysis, and regression management
Strong debugging skills in complex SoC environments
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field

Job Responsibility

Define and drive the overall SoC verification strategy for complex multi-billion transistor SoCs
Architect and develop scalable, reusable, and robust SoC verification environments using industry-standard methodologies
Lead end-to-end verification planning, execution, coverage closure, and sign-off activities
Drive power management verification, including validation of power state transitions, power controllers, reset sequencing, clock management, and power domain interactions
Lead low-power verification using UPF/CPF methodologies and ensure compliance with low-power design intent
Develop and review verification architectures, test plans, assertions, checkers, scoreboards, and coverage models
Collaborate closely with architecture, RTL design, firmware, emulation, validation, and physical design teams
Drive debug and root-cause analysis of complex SoC-level issues
Establish verification best practices, automation frameworks, and verification metrics
Support verification across simulation, emulation, FPGA prototyping, and post-silicon validation environments

What we offer

AMD benefits at a glance

Fulltime

ASIC Design Verification Engineer

Meet the Team: The Common Hardware Group (CHG) delivers the silicon, optics, and...

Location

India , Bangalore

Salary:

Not provided

Cisco

Expiration Date

Until further notice

Requirements

Bachelor’s Degree or equivalent experience in EE, CE, or other related field
7+ years of related ASIC design verification experience
Proficient in ASIC verification using UVM/System Verilog
Proficient in verifying sophisticated blocks, clusters and top level for ASIC
Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes

Job Responsibility

Architect block, cluster and top-level DV environment infrastructure
Develop DV infrastructure from scratch
Maintain and improve existing DV environments
Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus
Ensure complete verification coverage through implementation and review of code and functional coverage
Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist
Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance
Support testing of design in emulation
Lead all aspects of and manage the ASIC bring-up process

Fulltime

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RTL Emulation Engineer

Job Description

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