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Rtl design lead - cpu team

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AMD

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Location:
India , Bangalore

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Category:
IT - Software Development

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Salary:

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Job Description:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

Job Responsibility:

  • RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
  • Architect and design of power management features, cache, coherency
  • Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
  • Responsible for the inter IP integration issues resolution
  • Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem
  • Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design
  • Architecting, micro-architecting and documentation of the design features
  • Lead design team from all aspects of the RTL deliverables
  • Mentor the junior members of the RTL team to meet the team goals
  • Represents AMD to the outside technical community, partners and vendors

Requirements:

  • 6+ years of experience in Digital IP/ASIC design and Verilog RTL development
  • Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification
  • Well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation
  • Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects
  • Should possess expertise in front-end EDA tools sign-off and its flows
  • Familiarity with low power design and low power flow is an added plus
  • Ability to program with scripting languages such as Python or Perl is a plus
  • Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements
  • Proven interpersonal skills, leadership and teamwork
  • Excellent writing skills in the English language, editing and organizational skills required
  • Skilled at prioritization and multi-tasking
  • Good understanding of engineering terminology used within the semiconductor industry
  • Good understanding of digital design concepts
  • Knowledge of, or experience in, functional design verification or design is highly desired
  • Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering

Nice to have:

  • Familiarity with low power design and low power flow
  • Ability to program with scripting languages such as Python or Perl

Additional Information:

Job Posted:
March 25, 2026

Work Type:
Hybrid work
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