RTL Design Engineer

Role: RTL Design Engineer. What candidate will Be Doing: Strong expertise on Arteris Design Toolset (Like Mansour Amirfathi). At-least 5+ years of experience in Verilog Design. AMBA AXI bus along-with ARM or C based processor. Ensure customer satisfaction. Reporting to customers on daily or weekly progress effectively. NOC Architecture awareness. What we are looking for: PCIe System Expertise: Deep understanding and hands-on experience in PCIe system architecture, with an emphasis on physical layer design and specification. Ensure compliance with PCIe specifications, including but not limited to PIPE interface, LTSSM, 8b/10b and 128b/130b encoding, EIEOS intervals, equalization and electrical idle conditions. Deep understanding of PCIe retimer specification. Lead silicon bring-up activities, troubleshoot, and debug PCIe related issues. ASIC Design and Development: Design, implement, and verify ASIC components with a focus on PCIe physical layer requirements. Utilize Verilog and SystemVerilog for development, ensuring compliance with performance and design standards. SerDes Technology: Extensive knowledge of SerDes technology, including understanding its operation, design challenges, and integration into high-speed communication interfaces.