RTL Design Engineer Job at AMD (Bangalore)

Rtl Design Engineer

This exciting position in AMD's Silicon IP solutions & SOC group will provide th...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

A minimum of 8 years of experience is required
Proven experience in Silicon IP development process, methodologies, Design for Test methodologies
Experience with Verilog RTL design, VCS simulation tool, Perl/Shell scripting
Proven experience in contributing to complex silicon tapeouts
Detailed understanding and proven track record of developing any of the leading edge PCIe, Full featured DMAs, NVMe based Storage IP, networking IP solutions such as Ethernet, TCP/IP, RDMA IPs
Strong oral and written communication skills are essential
The ideal candidate will be a proactive contributor to the RTL design methodologies
Ability to work on complex issues where analysis situations or data requires an in-depth evaluation of variable factors
To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups
A Bachelor of Science Degree in Electrical Engineering or Computer Science, a master’s degree or equivalent experience is required

Job Responsibility

Define u-architecture from the architecture definition
Evaluating and executing design and development plans for IPs
RTL design, IP Integration & documentation
Participating in and acting as a senior technical reviewer for various u-architecture and implementation reviews within the development organization
Working with stakeholders to develop comprehensive testing plans including Compliance and Interop testing
Critically Review and provide feedback on the Design Implementations and Verification plans
Acting as technical mentor to junior engineers

Rtl Design Engineer

AMD-Xilinx is seeking a capable and motivated SOC Design Engineer to be part of ...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Digital design and experience with RTL design in Verilog/System Verilog
Solid understanding of DFT technologies and some experience with execution of DFT flows
Experience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
Experience in specifying timing constraints with several clock domains and modes
Basic experience with Synopsys Design Compiler and Primetime
Experience designing with multiple power domains and islands using UPF
Floor-planning and partitioning
TCL, Python, Perl scripting
Version control systems such as Perforce, IC Manage or Git
Understanding of FPGA architecture and implementation flow

Job Responsibility

Analyze existing design blocks for faults and vulnerabilities as application to automotive usage
Define and specify micro-architecture of future SOC building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements
RTL design and debug of functions in Verilog / System Verilog
Integration of hard macro or soft RTL IP into SOC top level
Power domain/island creation (with UPF)
Execution of quality checks to improve quality of RTL/UPF/SDC deliverables
Analysis of design metrics and making implementation choices to optimize PPA
Targeting SOC RTL to process technology
Facilitating DFx/MBIST instrumentation
Work with verification and physical design teams to achieve high quality design and successful tape out

RTL Design Engineer

As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips...

Location

United States , San Jose

Salary:

150000.00 - 275000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

At least 5 years of work experience in RTL development
Experience with high-speed digital logic
Proficiency in standard RTL design and synthesis tools
Familiarity with verification work and writing test benches
Are able to learn quickly about transformers and other aspects of modern artificial intelligence
Willing to start quickly

Job Responsibility

Implement a block to efficiently compute floating point math operators
Provide feedback to the uArch team to make sure blocks meet timing and area constraints

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office

Fulltime

RTL Design Engineer

Our client is a game-changer start-up that is designing and building the simulat...

Location

United States , San Francisco

Salary:

180000.00 - 250000.00 USD / Year

80Twenty

Expiration Date

Until further notice

Requirements

5+ years in RTL design or DV
Strong background in verification methodologies (UVM, SystemVerilog, testbench development)
Experience with synthesis, timing analysis, and debugging tools
Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor Graphics)
Strong communication skills for cross-functional collaboration for researchers who are not hardware experts

Job Responsibility

Lead the building of the hardest technical challenges in hardware design: Design challenges across RTL generation, verification, debugging, timing closure, specification alignment
Create RTL design and verification problems that mirror industry complexity and build realistic RTL codebases
QA environments and manage overseas hardware teams
Work directly with lab AI researchers to understand agent capabilities and training requirements
Have direct input on which hardware workflows we tackle next. You will decide which design or verification tasks are the highest-value targets for AI automation

What we offer

Paid relocation and sponsorship
Generous equity compensation

Fulltime

RTL Design Engineer

Role: RTL Design Engineer. What candidate will Be Doing: Strong expertise on Art...

Location

United States Of America , San Jose

Salary:

160000.00 - 180000.00 USD / Year

Arrow Electronics

Expiration Date

Until further notice

Requirements

Strong expertise on Arteris Design Toolset (Like Mansour Amirfathi)
At-least 5+ years of experience in Verilog Design
AMBA AXI bus along-with ARM or C based processor
Ensure customer satisfaction
Reporting to customers on daily or weekly progress effectively
NOC Architecture awareness
PCIe System Expertise: Deep understanding and hands-on experience in PCIe system architecture, with an emphasis on physical layer design and specification
Ensure compliance with PCIe specifications, including but not limited to PIPE interface, LTSSM, 8b/10b and 128b/130b encoding, EIEOS intervals, equalization and electrical idle conditions
Deep understanding of PCIe retimer specification
Lead silicon bring-up activities, troubleshoot, and debug PCIe related issues

What we offer

Medical, Dental, Vision Insurance
401k, With Matching Contributions
Short-Term/Long-Term Disability Insurance
Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
Paid Time Off (including sick, holiday, vacation, etc.)
Tuition Reimbursement
Growth Opportunities

Fulltime

Senior RTL Design Engineer

As a member of the Server SoC Group, you will help bring to life cutting-edge de...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Understanding SoC Design aspects that includes Clocking, IO, Latency, Reset, Fuse map, SoC Topology Networks
12+ years of experience in SoC Integration activities and definition of micro architecture
Experience with Verilog, Perl/Shell scripting, and all RTL quality checks
Triaging and debugging issues reported by Verification teams
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Work with SoC Architects, IP Design Teams and define micro architecture that includes clocking, reset, IO, Fuse
Implement SoC Design features/blocks, own connectivity across IP's
Work with Physical Design Team and deliver/triage all collaterals required for PD and implement SoC topology networks based on Full Chip floorplan and other Physical Design requirements
Own and drive RTL Quality checks/Audit that includes Lint/CDC/VCLP/Connectivity

Fulltime

Asic Rtl Design Engineer

Location

United States , Austin

Salary:

Not provided

Ericsson

Expiration Date

Until further notice

Requirements

BS in Electrical or Computer Engineering
Several years of hands-on, in industry RTL design experience at block and/or top level
Solid foundation in digital logic design
Strong command of C/C++, TCL, and/or Python
Proficiency in SystemVerilog, Verilog, or VHDL
Deep understanding of clock domain crossing (CDC) and static timing analysis (STA)
Hands-on experience with RTL linting and CDC tools — Synopsys SpyGlass and its peers

Job Responsibility

Write and verify RTL — clean, purposeful, production-bound code
Take designs from specification all the way to silicon CMOS circuitry
Analyze and optimize circuits on advanced process nodes
Wield state-of-the-art EDA tools to design and verify complex ASICs
Partner with engineers across disciplines on cross-functional initiatives
Collaborate with the backend team to close on synthesis, area, and timing

What we offer

Annual bonus opportunity
Choice of three medical plan options
Dental plan option
Company credits for medical and dental premiums
401(K) Plan with automatic 3% company contribution and matching contributions
Basic life insurance and basic accidental death and dismemberment coverage
Short-term and long-term disability coverage
Stock Purchase Plan
Minimum of 15 days of accrued vacation
Up to 3 personal days per year

Fulltime

Senior RTL Design Engineer – Accelerator IP

Join Ericsson’s Accelerator IP team in Austin, TX as a Senior RTL Design Enginee...

Location

United States , Austin

Salary:

117000.00 - 175000.00 USD / Year

Ericsson

Expiration Date

Until further notice

Requirements

Several years of RTL design in complex ASIC/IP environments
Expert SystemVerilog/Verilog skills
End-to-end ASIC flow mastery: coding, linting, CDC, synthesis, timing closure
Proven ability to distill DSP, FEC, or other L1 processing algorithms into high-performance hardware
Equally comfortable deep-diving into code and shaping high-level architecture strategies
A collaborative powerhouse who thrives in an intense, creative, close-knit environment

Job Responsibility

Transform high-level architectural vision into blazing-fast, reliable RTL (SystemVerilog/Verilog)
Take complete ownership of major IP blocks—specification, microarchitecture, RTL creation, synthesis, and delivery
Act as the go-to technical lead for verification, backend/PD, and architecture teams
Drive optimizations to balance power, area, and throughput without compromising innovation
Lead critical design decisions that steer the next generation of telecom hardware

What we offer

Choice of three medical plan options
Dental plan option
Company credits for medical and dental premiums
Ericsson US 401(k) Plan with automatic 3% company contribution and matching
Company credits for basic life insurance, basic accidental death and dismemberment coverage, short-term and long-term disability coverage
Option to participate in Ericsson’s Stock Purchase Plan
Minimum of 15 days of accrued vacation
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time

Fulltime

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Senior RTL Design Engineer – Accelerator IP

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