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This exciting position in AMD's Silicon IP solutions & SOC group will provide the individual with an opportunity to demonstrate strong technical leadership across the design hierarchy from architecture to Productization. Join us in providing innovative IP solutions as we embark on our journey into the cutting edge programmable logic based silicon designs by delivering the complex IP Solutions for multiple market segments
Job Responsibility:
Define u-architecture from the architecture definition
Evaluating and executing design and development plans for IPs
RTL design, IP Integration & documentation
Participating in and acting as a senior technical reviewer for various u-architecture and implementation reviews within the development organization
Working with stakeholders to develop comprehensive testing plans including Compliance and Interop testing
Critically Review and provide feedback on the Design Implementations and Verification plans
Acting as technical mentor to junior engineers
Requirements:
A minimum of 8 years of experience is required
Proven experience in Silicon IP development process, methodologies, Design for Test methodologies
Experience with Verilog RTL design, VCS simulation tool, Perl/Shell scripting
Proven experience in contributing to complex silicon tapeouts
Detailed understanding and proven track record of developing any of the leading edge PCIe, Full featured DMAs, NVMe based Storage IP, networking IP solutions such as Ethernet, TCP/IP, RDMA IPs
Strong oral and written communication skills are essential
The ideal candidate will be a proactive contributor to the RTL design methodologies
Ability to work on complex issues where analysis situations or data requires an in-depth evaluation of variable factors
To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups
A Bachelor of Science Degree in Electrical Engineering or Computer Science, a master’s degree or equivalent experience is required