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Our client is a game-changer start-up that is designing and building the simulations for agents to learn to design chips, and train AI on hardware automation. They are freshly funded, and have a very strong founding team. This is a full-time opportunity in San Francisco, CA, but paid relocation and sponsorship will be provided for the right candidate. This is a hybrid role combining deep semiconductor engineering and AI-driven simulation design. Founding hires will receive generous equity compensation.
Job Responsibility:
Lead the building of the hardest technical challenges in hardware design: Design challenges across RTL generation, verification, debugging, timing closure, specification alignment
Create RTL design and verification problems that mirror industry complexity and build realistic RTL codebases
QA environments and manage overseas hardware teams
Work directly with lab AI researchers to understand agent capabilities and training requirements
Have direct input on which hardware workflows we tackle next. You will decide which design or verification tasks are the highest-value targets for AI automation
Requirements:
5+ years in RTL design or DV
Strong background in verification methodologies (UVM, SystemVerilog, testbench development)
Experience with synthesis, timing analysis, and debugging tools
Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor Graphics)
Strong communication skills for cross-functional collaboration for researchers who are not hardware experts
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