Rtl Design Engineer Job at AMD (Hyderabad)

Rtl Design Engineer

AMD

Location:
India , Hyderabad

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Not provided

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Job Description:

AMD-Xilinx is seeking a capable and motivated SOC Design Engineer to be part of Front End SOC Design Team of next generation Adaptable Compute Acceleration Platform devices. You will take part in design and implementation of high-performance, low-power SOCs and SOC Chiplets targeting a wide range of applications as well as customer specific products. This high visibility and critical role will require technical leadership in developing microarchitecture, implementing functions in RTL, integrating IP from internal and external sources, ensuring quality and getting design ready for synthesis. You will also contribute to definition/evolution of SOC Design methodologies and processes for future projects.

Job Responsibility:

Analyze existing design blocks for faults and vulnerabilities as application to automotive usage
Define and specify micro-architecture of future SOC building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements
RTL design and debug of functions in Verilog / System Verilog
Integration of hard macro or soft RTL IP into SOC top level
Power domain/island creation (with UPF)
Execution of quality checks to improve quality of RTL/UPF/SDC deliverables
Analysis of design metrics and making implementation choices to optimize PPA
Targeting SOC RTL to process technology
Facilitating DFx/MBIST instrumentation
Work with verification and physical design teams to achieve high quality design and successful tape out
Collaborate with cross-functional teams to solve novel problems across multiple functional areas
Design and implement underlying Power Management, Clk/Rst, NOC and DFT infrastructures to ensure implementation tool requirements are met and are optimized for compile time and memory
Participate in tapeout checklists and reviews
Build automation (Python, TCL, Perl) to enhance productivity of self and team

Requirements:

Digital design and experience with RTL design in Verilog/System Verilog
Solid understanding of DFT technologies and some experience with execution of DFT flows
Experience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
Experience in specifying timing constraints with several clock domains and modes
Basic experience with Synopsys Design Compiler and Primetime
Experience designing with multiple power domains and islands using UPF
Floor-planning and partitioning
TCL, Python, Perl scripting
Version control systems such as Perforce, IC Manage or Git
Understanding of FPGA architecture and implementation flow
Strong verbal and written communication skills
Ability to organize and present complex technical information
Fluent in working with Linux environment

Additional Information:

Job Posted:
March 19, 2026

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