RTL Design Engineer Job at 80Twenty (San Francisco)

RTL Design Engineer

Our client is a game-changer start-up that is designing and building the simulat...

Location

United States , San Francisco

Salary:

180000.00 - 250000.00 USD / Year

80Twenty

Expiration Date

Until further notice

Requirements

5+ years in RTL design or DV
Strong background in verification methodologies (UVM, SystemVerilog, testbench development)
Experience with synthesis, timing analysis, and debugging tools
Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor Graphics)
Strong communication skills for cross-functional collaboration for researchers who are not hardware experts

Job Responsibility

Lead the building of the hardest technical challenges in hardware design: Design challenges across RTL generation, verification, debugging, timing closure, specification alignment
Create RTL design and verification problems that mirror industry complexity and build realistic RTL codebases
QA environments and manage overseas hardware teams
Work directly with lab AI researchers to understand agent capabilities and training requirements
Have direct input on which hardware workflows we tackle next. You will decide which design or verification tasks are the highest-value targets for AI automation

What we offer

Paid relocation and sponsorship
Generous equity compensation

Fulltime

Principal FPGA / RTL Design Engineer - Signal Processing

Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who ...

Location

United States , Irvine

Salary:

165000.00 - 250000.00 USD / Year

Silvus Technologies (International)

Expiration Date

Until further notice

Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields
Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs
Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Must be a U.S. Citizen due to clients under U.S. government contracts
All employment is contingent upon the successful clearance of a background check

Job Responsibility

Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering teams

Fulltime

Principal FPGA / RTL Design Engineer - Signal Processing

Participate in all aspects of the research and development process from concept ...

Location

United States , Los Angeles

Salary:

165000.00 - 250000.00 USD / Year

Silvus Technologies (International)

Expiration Date

Until further notice

Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields
Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs
Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Must be U.S. Person (U.S. Citizen, or Permanent Resident) due to clients under U.S. federal contracts
All employment is contingent upon the successful clearance of a background check

Job Responsibility

Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering Teams

Fulltime

Principal FPGA / RTL Design Engineer

The successful individual in this role will participate in all aspects of the re...

Location

United States , Irvine

Salary:

165000.00 - 250000.00 USD / Year

Silvus Technologies (International)

Expiration Date

Until further notice

Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant fields
Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or relevant fields
Demonstrated experience with fixed point binary arithmetic and digital signal processing designs
Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Must be a U.S. Citizen due to clients under U.S. government contracts

Job Responsibility

Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering Teams

Fulltime

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly skilled and experienced Principal Engineer to join our A...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field
8+ years of experience in ASIC development, with a proven track record of leading complex project
Hands on in IP / blocks / subsystem complex design in verilog / sysverilog
Strong digital design development and execution skills , solving bugs
Experience in grooming team of 1-4 engineers, interacting with many team
Deep expirience in debug , solving problem, see the architecture view, proposing solutions.
Hands-on experience with industry-standard EDA tools and design flows
Deep knowledge on PCIe, axi , DMA, AHB interfaces
Expertise in high-performance and low-power design techniques
Excellent communication skills, both verbal and written, with the ability to articulate complex technical concepts clearly

Job Responsibility

Design and implements IPs and subsystems
Dealing the best of class IPs for all SanDisk products

Fulltime

ASIC RTL Design Engineer

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate, implement, and verify RTL code for complex ASICs
Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Lead design reviews and provide mentorship to junior engineers
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

RTL Design Engineer

Our client is a game-changer start-up that is designing and building the simulat...

Location

United States , San Francisco

Salary:

180000.00 - 250000.00 USD / Year

80Twenty

Expiration Date

Until further notice

Requirements

5+ years in RTL design or DV
Strong background in verification methodologies (UVM, SystemVerilog, testbench development)
Experience with synthesis, timing analysis, and debugging tools
Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor Graphics)
Strong communication skills for cross-functional collaboration for researchers who are not hardware experts

Job Responsibility

Lead the building of the hardest technical challenges in hardware design: Design challenges across RTL generation, verification, debugging, timing closure, specification alignment
Create RTL design and verification problems that mirror industry complexity and build realistic RTL codebases
QA environments and manage overseas hardware teams
Work directly with lab AI researchers to understand agent capabilities and training requirements
Have direct input on which hardware workflows we tackle next. You will decide which design or verification tasks are the highest-value targets for AI automation

What we offer

Paid relocation and sponsorship
Generous equity compensation

Fulltime

Senior FPGA / RTL Design Engineer - Signal Processing

Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Direc...

Location

United States , Irvine

Salary:

125000.00 - 195000.00 USD / Year

Silvus Technologies (International)

Expiration Date

Until further notice

Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 6 years of demonstrated experience in FPGA design
4 years of FPGA design experience with a Master of Science degree
2 years of FPGA design experience with a PhD
Demonstrated experience with fixed point binary arithmetic and digital signal processing designs
Proven expertise working with multiple clock-domain, high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Must be a U.S. Citizen due to clients under U.S. government contracts
All employment is contingent upon the successful clearance of a background check

Job Responsibility

Digital design architecting for wireless communication projects
Fixed point design of signal processing blocks while working with systems engineers
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering teams

Fulltime

RTL Design Engineer

80Twenty

Location:
United States , San Francisco

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
January 05, 2026

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