RTL Design Engineer

• Develop and maintain block level RTL IP and MP subsystems’ feature spec, micro-architecture, synthesizable RTL design methodology and infrastructure
• Develop and debug RTL designs using C-DPI directed test methodology, and/or using verification team’s testbenches and tests, and achieve design feature closure (feature spec vs. coverage metrics)
• Triage regressions, debug specific simulations, analyze coverage, and work/resolve technical issues with design, verification, and other teams to achieve design feature and design rule closures (linting, timing, DFT, DFP and other rules)
• Participate in verification testbench and test plan specification, influence testbench architecture development (design for verification aspect), review and improve feature and coverage test plans
• Debug and resolve integration issues with SoC Integration, SoC DV and post-silicon validation teams
• Provide technical leadership in IP functionality and design methodology development as well as critical problem resolution if as advanced level team members

• Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field
• Proven understanding of CPU and MP subsystem architecture, datapath accelerator RTL microarchitecture, as well as FPGA based emulation and prototyping methodology
• Proficient in Verilog, System Verilog (an extra asset), and scripting (using Tcl, Ruby, Perl, Python and Makefile)
• Excellent knowledge about state-of-art RTL design and verification methodology and best practices, and C-DPI test design
• Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
• Proven experience with ASIC design tools: synthesis, linting, simulation, debugging, power aware simulation, etc.
• Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates

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