RTL & Co-design Engineer Job at OpenAI (San Francisco)

ASIC Design Architect

We are seeking a highly experienced ASIC Networking Architect to join our archit...

Location

United States

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science. Ph.D. is a plus
Minimum 10+ years in ASIC architecture, with a focus on networking, computing, or high-performance data processing
Strong Background in: Computer Architecture: Multicore processing, memory hierarchy optimizations, hardware-software co-design
Networking Protocols: Ethernet, TCP/IP, BGP, MPLS, VXLAN, QoS, congestion control mechanisms
ASIC Development Lifecycle: RTL design (Verilog/SystemVerilog), verification methodologies (UVM), synthesis, P&R constraints, and tape-out experience
High-Speed Interfaces: PCIe Gen6, SerDes, CXL, HBM integration
Security & Virtualization: Hardware acceleration for secure packet processing, hypervisor optimizations, and virtual network functions
Leadership & Collaboration Skills: Experience working with cross-functional teams spanning hardware, software, and systems
Strong problem-solving and analytical abilities with a track record of delivering complex ASIC projects

Job Responsibility

Architecture Definition: Develop the micro-architecture and high-level design of networking ASICs, ensuring alignment with product goals, performance targets, and industry standards
Networking Protocols & Technologies: Design ASICs that support Ethernet (200G/400G/800G+), Programmability, and AI-driven networking enhancements
Computer Architecture & Memory Subsystems: Optimize packet processing pipelines, caching strategies, memory architectures (HBM, DDR, TCAM, SRAM), and interconnect fabrics for high-bandwidth, low-latency performance
ASIC Design Collaboration: Work with logic design, verification, and physical design teams to ensure smooth RTL implementation, synthesis, timing closure, and signoff
Performance Analysis & Optimization: Use simulation and emulation tools to model ASIC performance, validate system throughput, and optimize power/performance trade-offs
Security & Reliability Features: Implement security mechanisms such as MACSec, IPsec, and deep packet inspection for trusted networking solutions
Industry Trends & Future Technologies: Stay ahead of advancements in disaggregated networking, hardware acceleration (DPUs, SmartNICs), AI-driven networking, and software-defined infrastructure to influence long-term ASIC roadmaps
Technical Leadership: Drive architectural innovation and mentor engineers in design methodologies, ASIC lifecycle best practices, and system integration challenges
Influence Business decisions: Leverages recognized domain expertise, business acumen, and experience to influence decisions of executive business leadership, outsourced development partners, and industry standards groups

What we offer

Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing
Personal & Professional Development: We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division
Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good

Fulltime

SoC Systems Software Engineer

AWS designs custom SoCs (System on Chips) that power the world's largest machine...

Location

United States , Cupertino; Austin

Salary:

168100.00 - 261500.00 USD / Year

Amazon

Expiration Date

Until further notice

Requirements

6+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
Experience as a mentor, tech lead or leading an engineering team
7+ years of professional experience developing firmware, drivers, runtime software, or low-level systems software for custom hardware (SoCs, ASICs, GPUs, CPUs, FPGAs)
Experience programming in C++, Python, and/or Rust (preference for at least 2)
Knowledge of SoC, CPU, GPU, and/or ASIC architecture and micro-architecture

Job Responsibility

Develop and own components of our SoC models, both single-chip and at the datacenter-scale level
Debug complex hardware/software interactions across the full software stack — from register-level bring-up on functional models and emulators, to performance analysis on live silicon
Collaborate with chip architects, RTL designers, modelers, compiler engineers, and ML framework teams to co-design and validate the hardware/software interface
Contribute to the design of hardware features by providing a software perspective early in the chip development cycle
Build tooling, test infrastructure, and automation that accelerates development for yourself and your teammates

What we offer

health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
401(k) matching
paid time off
parental leave
sign-on payments
restricted stock units (RSUs)

Fulltime

C++ Simulation Engineer, GPU Modeling

AMD is looking for a C++ Simulation Engineer, GPU Modeling passionate about driv...

Location

Canada , Markham

Salary:

88000.00 - 132000.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Proven hands-on object oriented programming experience in C/C++
Experience or familiarity with advanced text editors and IDEs
Good understanding of computer organization/architecture
Undergrad degree required
Bachelors or Masters degree in Computer Science or Computer Engineering preferred

Job Responsibility

Drive the development of C/C++ simulation models for silicon architecture and algorithm evaluation, performance analysis and hardware verification
Partner with cross-functional teams such as HW/SW Co-design, RTL design, verification, emulation, post silicon validation, firmware and software development, in the use and support of building ASIC architecture and simulation models to ensure first pass silicon success and rapid deployment
Develop and debug complex code, on a large-scale codebase and version control systems

Fulltime

C-Simulation Engineer, GPU Modeling

AMD is looking for a C-Simulation Engineer passionate about driving the cutting-...

Location

United States , Orlando, Florida

Salary:

98400.00 - 147600.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Proven hands-on object oriented programming experience in C/C++
Experience or familiarity with advanced text editors and IDEs
Good understanding of computer organization/architecture
Undergrad degree required
Bachelors or Masters degree in Computer Science or Computer Engineering preferred

Job Responsibility

Drive the development of C/C++ simulation models for silicon architecture and algorithm evaluation, performance analysis and hardware verification
Partner with cross-functional teams such as HW/SW Co-design, RTL design, verification, emulation, post silicon validation, firmware and software development, in the use and support of building ASIC architecture and simulation models to ensure first pass silicon success and rapid deployment
Develop and debug complex code, on a large-scale codebase and version control systems

Fulltime

Physical Design Engineer

In this role, you will be responsible for the implementation and signoff of comp...

Location

China , Beijing

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Full chip floorplan experience
Scripting language experience: Perl, Tcl, Python
Exposure to leadership or mentorship is an asset
Experience with high-performance CPU/GPU/AI accelerator physical design in advanced nodes (7nm and below)
Hands-on experience with low-power design techniques (power gating, multi-voltage, DVFS) and UPF/CPF flow
Familiarity with 3D-IC or chiplet-based design methodologies and associated tool flows
Knowledge of package-aware floorplanning and system-level co-design considerations
Experience with machine learning applications in physical design (e.g., auto-placement, routing prediction)
Prior exposure to design for testability (DFT) integration and post-silicon debug support
Proven track record of successful tape-outs in high-complexity SoC projects

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features
RTL-to-GDSII Implementation – Execute full physical design flow including synthesis, floorplanning, placement, CTS, routing, and signoff
Timing & Power Closure – Perform static timing analysis (STA), power analysis, and optimize designs to meet timing, power, and area goals
Physical Verification – Run DRC, LVS, and other verification checks to ensure design manufacturability
Methodology & Automation – Develop and maintain scripts to improve design efficiency and quality
Cross-functional Collaboration – Work with frontend, DFT, and CAD teams to resolve design issues and implement methodology improvements
Documentation & Reporting – Create clear documentation and regularly report progress to project stakeholders