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RTL & Co-design Engineer

United States, San Francisco 225000.00 - 445000.00 USD / Year · Job Posted February 21, 2026
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Job Description

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.

Job Responsibility

  • Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems
  • Contribute to architectural studies including performance modeling and feasibility analysis
  • Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit
  • Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration
  • Build and review performance and functional models to validate design intent
  • Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.

Requirements

  • Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization
  • Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out
  • Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems
  • Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies
  • Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams
  • Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits
  • Passion for building industry-leading massive-scale hardware systems
  • To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

What we offer

  • Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
  • Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
  • 401(k) retirement plan with employer match
  • Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
  • Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
  • 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
  • Mental health and wellness support
  • Employer-paid basic life and disability coverage
  • Annual learning and development stipend to fuel your professional growth
  • Daily meals in our offices, and meal delivery credits as eligible
  • Relocation support for eligible employees
  • Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided
  • Offers Equity
  • Performance-related bonus(es) for eligible employees.

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