Quantum ASIC Project Lead

• Lead ASIC projects for Microsoft's quantum solutions, partnering with IP owners to develop IP blocks, integrating them at the SoC top level, and working with Digital Verification (DV), Synthesis, Design-For-Test (DFT), and Physical Design teams to prepare the SoC for tapeout
• Own post-silicon test and scan, validation, device characterization, and the path to production
• Coordinate the work of engineers, contractors, and contracting agencies delivering portions of the SoC
• Drive microarchitecture and Register-Transfer-Level (RTL) design, coding, and verification of complex IP blocks, with an emphasis on meeting stringent power, performance, and timing goals
• Develop constraints, power intent, synthesis, and static checks including LINT, Clock-Domain Crossing, and Reset-Domain Crossing
• Build basic test benches and support verification, DFT, and post-silicon validation activities alongside verification and product teams
• Collaborate effectively with architects, analog mixed-signal designers, verification engineers, physical design and DFT teams, and other front-end designers
• Set up and manage databases and flows for SoC and IP repositories
• Align development methodologies across teams and drive continuous improvement of RTL processes for at-scale execution

• Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment
• OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
• OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
• OR equivalent experience
• Ability to meet Microsoft, customer and/or government security screening requirements
• Ability to leverage AI tools to drive innovation and efficiency
• Ability to work in an 'AI-first' environment using modern AI tools
• 15+ years of experience in digital design, including microarchitecture specification and RTL coding in Verilog and SystemVerilog
• 8+ years of hands-on experience with synthesis, timing constraints, and Power/Performance/Area (PPA) trade-offs
• 5+ years of experience leading SoC integration through successful ASIC tapeouts
• Demonstrated proficiency in RTL design and front-end design methodologies
• Proven track record closing Clock-Domain Crossing (CDC), Reset-Domain Crossing (RDC), and LINT checks, plus post-silicon debug
• Experience integrating Central Processing Units (CPUs), analog IP, and standard bus interfaces such as Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI), Inter-Integrated Circuit (I2C), Serial Peripheral Interface (SPI), and Joint Test Action Group (JTAG)
• Experience coordinating and managing SoC execution with external vendor teams
• Proficiency scripting in Python and/or Perl to automate engineering and design workflows
• Experience designing and building AI agents or copilots that assist with engineering tasks such as environment setup, log triage, or measurement report generation
• Track record of integrating AI-assisted solutions into design flows to improve productivity and quality

Certain roles may be eligible for benefits and other compensation