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Process Engineer Metrology & Yield Enhancement

United States, Tempe · Job Posted June 04, 2026
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Job Description

This position is responsible for overseeing the development of a 150 mm wafer line based on QCi’s thin film lithium niobate (TELN) technology. The successful candidate will work in close collaboration with both the process development and integration team as well as the quantum optics team to develop and continuously improve high volume manufacturable metrology and test point processes for our TFLN products. These processes are designed to monitor line health, feed forward critical process and equipment data to optimize product yields, This candidate also plays a key role in facilitating short term SWAT teams when urgent line impacting defect investigations arise. The candidate will be responsible for designing, developing, deploying and optimizing metrology processes for measuring TFLN devices to achieve safety, quality, cost, and delivery goals for QCi and its customer products. The candidate will work closely with a team of process and equipment engineers and technicians to continuously improve their workflow with the goal of enhancing yield of TFLN devices and creating robust reliable manufacturing processes. Furthermore, the candidate will coordinate the factory metrology and diagnostic equipment calibration program.

Job Responsibility

  • Lead the development and optimization of photolithography and/or wet processes for compound semiconductor applications
  • Drive process integration and improvement initiatives to enhance device performance and yield
  • Work closely with the process team in the cleanroom to optimize associated metrology measurements in the fabrication flow of TFLN chips
  • Facilitate the transition of research level chip scale production, to low, to middle volume manufacture at wafer scale
  • Utilize advanced metrology tools such as CD SEM, AFM, ellipsometry, profilometry, XPS, XRD, and optical interferometry for process characterization and defect analysis
  • Work closely with integration, production, and device engineering teams to integrate photo and/or wet processes into the overall semiconductor fabrication flow
  • Troubleshoot process deviations, particle contamination, and unit performance issues, implementing corrective actions and continuous improvement strategies
  • Establish and maintain SPC for process monitoring and optimization
  • Evaluate and qualify new photo and/or wet chemistries, masks, hardware configurations, and process automation tools
  • Develop and document process recipes, work instructions, and standard operating procedures (SOPs)
  • Mentor junior engineers and provide /or leadership in semiconductor photo, wet, mask, and associated metrology

Requirements

  • 5+ years’ experience in Process Development and Continuous Improvement through predictive/preventive metrology measurement & yield enhancement analysis programs
  • Optical modeling and analysis for coherent micro-optical and photonic systems
  • Apply advanced statistical and analytical methods to identify, quantify, and control risk in complex manufacturing environments
  • Translate PFMEA outputs into actionable process controls
  • Define and implement the inspection methods, calibration systems, and SOPs
  • Manage calibration programs and maintain compliance with ISO and customer quality standards
  • Deploy advanced sampling strategies, SPC controls, Cp/Cpk, GR&R, and integrate Minitab/JMP analytics into daily operations
  • Experience with process characterization and metrology techniques such as/or equivalent SEM, AFM, KLA Optical profiler, Stylus profiler, microscope, spectral analysis, and ellipsometry

Nice to have

  • 10+ years’ experience in Metrology & Yield Enhancement Process development, process integration
  • Experience and understanding of microfabrication for photonics devices, process integration, photonic materials properties and modification, and the incorporation of MEMS and electronic devices
  • Apply large-scale data analytics to Track-and-Trace datasets
  • Experience with heterogeneous bonding between wafers and chips
  • Experience working with 5S, and 6 Sigma

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