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Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a principal design verification engineer to work in the dynamic Microsoft Artificial Intelligence Silicon Engineering (AISiE) team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment. Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Job Responsibility:
Own or lead verification of complex flows at the SOC, subsystem, or IP levels
Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios
Learn about the design and interact with partner teams to define verification strategies and test plans
Develop verification environments and run and debug simulations to drive quality
Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
innovate to improve verification efficiency through methodologies or tools
Coach and mentor others in your areas of expertise
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion
Requirements:
12+ more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s
Experience with verification for multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff in UVM or C++
Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
Scripting language such as Python or Perl
Nice to have:
Hands on experience in Formal property verification
knowledge in high-speed protocols like DDR/HBM, PCIe, Ethernet