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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CCDO team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal STA Engineer to join the team.
Job Responsibility:
Own subchip construction timing constraint methodology and support the physical design team
Own signoff timing constraint management methodology and support. Do constraint verification
Drive IP and full-chip level timing closure for various SoC projects
Drive solutions for critical timing paths by collaborating with back end, logic, floorplan and other relevant owners
Ensure quality by setting up a robust design signoff methodology covering areas such as variation, yield analysis, transistor aging, interconnect extraction, and noise analysis
Contribute to full-chip level timing model build, flow maintenance and release process
Improve design execution efficiency through flow automation and indicator generation
Influence STA tools, flows, signoff accuracy and modeling efficiency with a data driven approach by engaging in various advanced EDA feature pioneering
Make good independent technical trade-offs between power, area, and timing
Provide technical leadership and collaborate across teams to come up with the best solution possible with a One Microsoft mindset
Apply your growth mindset to learn and adapt in a complex and dynamic environment
Requirements:
Candidate must have at least a bachelor’s degree in Electrical Engineering, Computer Engineering, or a related degree or equivalent work experience
Strong circuit design background with understanding in variation, spice modeling, aging simulations, yield analysis
Solid experience with EDA tools such Static Timing Analysis, Noise Glitch analysis, interconnect extraction
Understanding in managing timing constraints, exceptions, IP constraint promotion, efficient constraints practices etc.
Excellent communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Nice to have:
Strong problem-solving and data analysis skills
Strong automation skills using scripting languages such as Python, Perl, TCL
In-depth understanding of design tradeoffs for power, performance, and area
Experience and knowledge of formal equivalency checks, LP, UPF, and reliability
Experience in floorplan optimization taking design convergence, power domain crossing and die area into account