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Principal Silicon Design Engineer

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AMD

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Location:
Malaysia , Penang

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Category:
IT - Software Development

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Contract Type:
Not provided

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Salary:

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Job Description:

As CAD Manager you will be responsible for leading and optimizing the EDA environment for Project CAD team in the Adaptive & Embedded Computing Group (AECG). You will oversee the complete SCH-to-GDS flow, manage tool deployments, and drive methodology development across multiple semiconductor projects. This is an opportunity to shape the technical direction of critical IC design workflows and lead a team of skilled CAD engineers. You will advise on tools selection, and interface with various EDA tool vendors and foundries to run the EDA tools, PDKs and other files necessary for the Silicon Development Team to operate efficiently. You will be responsible for defining and creating a unified environment that sets the versions of the tools, PDK and design for every individual chip in development. Additionally, you will interact with the various Silicon development teams who will be requesting newer versions of the tools, and raise trouble tickets with CAD vendors as needed.

Job Responsibility:

  • Lead and manage the CAD infrastructure team supporting multiple IC design projects
  • Establish and maintain standardized design flows and methodologies
  • Implement and support customized CAD flows for Fabric design groups
  • Enable the team in meeting the design and development targets by working closely with external tool vendors
  • Develop tools flows methodologies on digital back-end domains, sign-off flows for timing, power, EM/IR, DRC/LVS/DFM, etc.
  • Improve engineering efficiency while improving design quality in IP release process
  • Be single point contact for bugs and issues for custom and analog physical design team
  • Build flow in TCL, Python to ensure quality and faster executions
  • Understand different methodologies used across industry to adopt best practices
  • Leverage and deploy AMD AI systems to design teams

Requirements:

  • 10+ years of silicon EDA and/or digital ASIC design experience
  • PPA Power Performance Area Optimization
  • Virtuoso based custom Layout tools and flows
  • Calibre extraction flows, Totem & Redhawk for EM/IR
  • TCL, Python, PERL, or other scripting languages
  • 2+ years in one or more of these tools: Design compiler, IC Compiler, Fusion Compiler, Cadence Virtuoso and Custom Compiler
  • Physical aspect of VLSI designs
  • Strong written and verbal communication skills
  • Bachelors or Masters degree in Computer Engineering/Electrical Engineering

Additional Information:

Job Posted:
January 03, 2026

Work Type:
Hybrid work
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