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We are seeking a seasoned Signal and Power Integrity Engineer with expertise or significant interest in System SIPI. This senior role will stretch you as you lead Power Integrity teams in development directions and design trade offs.
Job Responsibility:
Responsible for Signal Integrity and Power Integrity simulations at feasibility, pre-layout, post-layout phases of AECG characterization board and demo board design. Establish design and layout guidelines
Responsible for coordinating with HW design team, layout team, NPI and manufacturing vendors to resolve SI/PI related issues
Responsible for end-to-end channel simulations for multi gigabit serial lines like 56Gbps, 112Gbps and beyond
Responsible for PI analysis simulations of HBM/ /DDR4/LPDDR4/DDR5/LPDDR5 and other memory buses
Responsible for characterizing the various interfaces in the product and verifying the simulations against measurements
Responsible for preparation of and implementing checklists for various stages of PCB development
Worked with architecture team, package design team and PCB design team for future PCB technology
Update the SIPI design and analysis flow and automate the process
Requirements:
MS or PhD in Electrical Engineering
Excellent analytical and problem-solving skills along with attention to details
Need a self-starter, someone able to drive tasks independently and efficiently to completion
Strong/effective communication skills
Enthusiastic team-first mentality
Experience with PCB, Package and IC level power delivery networks
Experience in silicon packaging and PCB design for signal and power integrity
Experience with high-speed digital signaling interfaces such as PCIE, GDDR6, HDMI
Expertise in electrical modeling EDA and AMS tools such as ADS, HFSS, SIwave, HSPICE
Expertise in electromagnetic theory and circuit analysis
Experience with programming in Python, C++, Matlab