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Principal Quantum Systems Digital Design Engineer

https://www.microsoft.com/ Logo

Microsoft Corporation

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Location:
United States , Redmond

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Contract Type:
Not provided

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Salary:

139900.00 - 274800.00 USD / Year

Job Description:

Microsoft is the world’s center of expertise on topological quantum computing. We are building a scaled, fault‑tolerant quantum computer grounded in topological qubits and integrated end‑to‑end with the Azure Quantum software stack. As a Principal Quantum Systems Digital Design Engineer, you’ll collaborate closely with quantum physicists, systems software, RF/EE, and manufacturing/production to define, design, and deliver FPGA‑based, ultra‑low‑latency digital subsystems that sit at the heart of our topological quantum engine - spanning readout classification, error‑decoder acceleration, room‑temperature front‑ends for cryogenic control, high‑speed interconnects, and precision clocking networks. Your work will directly impact logical‑qubit stability, throughput, and system scale.

Job Responsibility:

  • Design & implement RTL for streaming, low‑latency pipelines (e.g., readout classifiers, syndrome aggregation, and QEC decoder kernels) in Verilog/SystemVerilog, including resource/performance trade‑offs and power/thermal considerations
  • Design and implement high‑speed interconnects between subsystems (AXI4/AXI‑Stream, JESD204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring‑up, and throughput/latency tuning
  • Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi‑domain timing closure, async FIFOs, metastability analysis) for deterministic performance
  • Co‑design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams
  • contribute to system‑level design reviews
  • Verification and validation: develop simulation and constrained‑random tests (SV/UVM or equivalent), build on‑board diagnostics (ILA/ChipScope), and execute lab bring‑up with scopes, VNAs, LA/SC, and RF instruments
  • Tool flow & CI: own synthesis/implementation (Vivado/Vitis or Quartus/Prime), timing sign‑off, and reproducible, scripted builds (Tcl/Python) integrated with Git/Azure DevOps CI/CD
  • Quality & documentation: produce clear design docs, interface specs, and bring‑up guides
  • participate in rigorous code/design reviews and post‑silicon/post‑fabrication retros

Requirements:

  • Doctorate in Physics, Electrical/Computer Engineering, or related field AND 3+ years experience in industry or in a research and development environment
  • OR Master's Degree in Physics, Electrical/Computer Engineering, or related field AND 4+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Physics, Electrical/Computer Engineering, or related field AND 6+ years experience in industry or in a research and development environment
  • OR equivalent experience
  • 6+ years programming experience in related programming languages
  • 6+ years experience in a collaborative environment
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
  • Ability to work in an "AI first" environment using modern AI tools to accelerate discovery through hardware development
  • Familiarity with designing and building AI agents/copilots that assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval

Nice to have:

  • 8+ years building production FPGA designs in Verilog/SystemVerilog (or VHDL), including synthesis, P&R, and static timing analysis on Xilinx/AMD (UltraScale+/Versal/RFSoC) and/or Intel platforms
  • Proven delivery of low‑latency, streaming datapaths (DSP, filtering, classification, or decoder‑like pipelines) with tight timing closure at high clocks
  • Hands‑on with high‑speed I/O and protocols: AXI4/AXIS, JESD204(B/C), Aurora, multi‑gig SERDES
  • competent in link bring‑up, eye margins, and error budget analysis
  • Proficiency in clocking/CDC fundamentals and experience with multi‑clock, multi‑reset systems
  • Verification skills (simulation, assertions, testbenches
  • UVM a plus) and lab debug using ILA/ChipScope, scopes, LA, and RF test gear
  • Familiarity with RFSoC architectures (data converters, JESD links) and/or heterogeneous co‑processing with CPUs/GPUs
  • Comfort working across HW/SW boundaries (DMA perf tuning, drivers, gRPC/REST control surfaces, telemetry/observability) and with scientific instrumentation
  • Experience accelerating decoders (e.g., graph/union‑find/MWPM‑style or LDPC‑class techniques), streaming inference/classification, or similar real‑time algorithms
  • Exposure to HLS (C/C++/HLS kernels) and mixed HLS/RTL systems
  • formal verification
  • Background in signal processing/control or quantum control/readout concepts (nice to have
  • curiosity and fast learning are more important)
  • Experience with Windows & Linux, VS Code, Git/GitHub, Azure DevOps CI/CD
  • scripted builds (Tcl/Python)
  • design docs + code reviews + comprehensive testing are part of our quality bar

Additional Information:

Job Posted:
March 18, 2026

Employment Type:
Fulltime
Work Type:
Hybrid work
Job Link Share:

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