Principal Physical verification engineer Job at Sandisk (Hyderabad)

New

Principal Engineer Physical Design

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

Malaysia , Gelugor

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

BS/BE/BTech/MS/ME/MTech in Electronics or Microelectronics/VLSI, or Electrical Engineering
Min 15+ years of experience in semiconductor design
Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams
Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, EMIR closure and physical verification
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of complex partitions/subsytems through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification
Own complete PD execution of Sub-systems/Sub-chips instantiating/integrating multiple other physical partitions
Implement robust clock distribution solutions using appropriate methods that meet design requirements
Have close collaboration with RTL team (RTL2PD liaison) to help drive and resolve design issues related to block closure
Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach
Make independent and good technical trade-off decisions between power, area, and timing (PPA)
Lead, guide and coordinate with all sub-partitions PD owners to be able to take Subsystem/Subchip through PD (construction through signoff) closure
Collaborating and influencing various aspects of PD Methodology will also be key requirement in this role
Additionally drive key pieces of PD implementation methodology or specific areas such as Clocking/Low power optimization/Power & Performance methodology
Partner closely with PD flow/CAD team and PD methodology team

Fulltime

Principal Quantum Engineer

Microsoft’s mission is to empower every person and every organization on the pla...

Location

United States , Redmond

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Bachelor's Degree in Electrical Engineering, Materials Science, Physics or related field AND 8+ years’ experience in industry or in a research and development environment
OR Master's Degree in Electrical Engineering, Materials Science, Physics, or related field AND 6+ years’ experience in industry or in a research and development environment
OR Doctorate in Electrical Engineering, Materials Science, Physics, or related field AND 3+ years’ experience in industry or in a research and development environment
OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check
Citizenship & Citizenship Verification
Ability to leverage AI tools to drive innovation and efficiency
Ability to design and build AI agents/copilots
Effective interdisciplinary technical communication skills

Job Responsibility

Lead cross-functional technical work across materials, fabrication, and electrical characterization
Improve operational efficiency and balance and prioritize resources across projects
Review data to glean actionable insights to improve device and material performance
Collaborate effectively across teams, demonstrating clear communication
Embody our culture and values

Fulltime

Staff Controls Engineer

The Staff Controls Engineer reports to the Chief Technology Officer and serves a...

Location

United States , Fargo

Salary:

Not provided

CorVent Medical

Expiration Date

Until further notice

Requirements

Ph.D. or M.S.E. in Control Engineering, Electrical Engineering, or Applied Physics
Minimum 10+ years of experience designing feedback control systems, preferably in medical or safety-critical applications
Mastery of feedback control theory: continuous, discrete, state-space, and frequency-domain design
Deep experience in: Nonlinear control methods (windup prevention, direct and indirect adaptive control, nonlinear optimization)
Filter design (IIR, FIR, LP, HP, BP, notch, differentiators)
Uncertainty & sensitivity analysis
propagation of error
Skilled in Matlab/Simulink modeling, scripting, and automatic code generation for embedded systems
Demonstrated success leading technical teams and coordinating cross-functional projects
Excellent communication, documentation, and leadership skills

Job Responsibility

Provide technical leadership for all control system design, architecture, and integration activities
Supervise and mentor the Principal Control Engineer and other team members, ensuring quality, consistency, and regulatory compliance
Define performance objectives for dynamic control of ventilator subsystems (blower, valves, sensors, patient interface)
Lead model-based design (Matlab/Simulink, Stateflow) for algorithm development, verification, and code generation
Direct the synthesis, simulation, and validation of feedback and feedforward control systems, including nonlinear and adaptive methods
Conduct uncertainty and sensitivity analyses, including propagation of error for dynamic system robustness
Specify and validate filter designs (IIR, FIR, low-pass, high-pass, band-pass, notch, differentiators) for signal conditioning and sensor processing
Apply advanced estimation and prediction methods: least squares, observers, algebraic methods, and Kalman filters
Lead formal design reviews, test planning, and risk management activities per ISO 14971 and FDA design control
Communicate technical status, issues, and progress to the CTO and executive leadership

Fulltime

New

Principal Controls Engineer

Own the control architecture for Mach’s fixed-wing aircraft. You’ll lead the des...

Location

United States , Huntington Beach

Salary:

220000.00 - 250000.00 USD / Year

Mach Industries

Expiration Date

Until further notice

Requirements

Bachelors in Engineering, Physics, Mathematics
8+ years designing and fielding flight control systems for fixed-wing aircraft or high-performance UAVs, including flight test
Deep knowledge of flight dynamics, stability/controllability, and actuator/sensor modeling
Proficiency in modern C++ for embedded real-time implementations
strong MATLAB/Python for modeling, ID, and analysis
Demonstrated ownership of verification workflows (SIL/HIL), requirements traceability, and safety reviews
Familiarity with modern software workflows (git, code review, issue tracking) and data/telemetry analysis

Job Responsibility

Define control system architecture and requirements for fixed-wing vehicles (primary flight control, envelope protection, autothrottle/energy mgmt, and mode logic)
Design and implement control laws accounting for actuator limits, time delays, and sensor noise
Lead system identification and aerodynamic model development from wind-tunnel, CFD, and flight-test data
build accurate linearizations
Develop fault-tolerant and reconfiguration strategies (sensor/actuator FDI, control allocation, redundancy mgmt) with graceful degradation
Own verification & validation: SIL/HIL campaigns, Monte Carlo, and flight-readiness criteria
establish performance dashboards
Drive flight-test planning and execution
analyze logs, tune controllers, and iterate safely and quickly
Mentor the controls team, set technical standards, conduct design/code reviews, and influence roadmap and milestones

What we offer

Offers Equity
healthcare
dental and vision plans
retirement savings
paid time off
funds for continuing education, training, and career growth

Fulltime

Principal Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This role will require access to information that is controlled for export under export control regulations
10+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure
8+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs
5+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug
5+ experience in Designing Fabric/Network On Chip or Networking ASICs or Complex Control Logic

Job Responsibility

Part of the design team driving many facets of high performance, high bandwidth designs
Working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis, and System on Chip (SOC) integration on different subsystems
Interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec

Fulltime

New

Principal Engineer, ASIC Development Engineering (PD Methodology & CAD Flow)

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...

Location

India , Hyderabad

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

8+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs
Deep, hands-on understanding of complete PD flow, including: Synthesis, Logical Equivalence Checking (LEC), DFT insertion and integration, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis
Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA
Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes
M.Tech in VLSI Design or a related field (or equivalent industry experience)
Proficiency in scripting and automation using TCL, Perl, and/or Python
Experience working in multi-project, high-complexity environments with tight schedules

Job Responsibility

Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices
Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions
Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence
Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules
Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability
Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity
Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges

Fulltime

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
9+ years of experience in digital design, with a focus on RTL design for complex SoCs
Deep expertise in Verilog/SystemVerilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Experience with synthesis, static timing analysis, and DFT concepts
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Proven track record of leading technical teams and delivering successful silicon
Excellent analytical, problem-solving, and communication skills
Passion for innovation and delivering high-quality, scalable solutions

Job Responsibility

Define and review SoC architecture and design specifications
Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
Contribute to IP selection, evaluation, and integration in SoC designs
Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels

Fulltime

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
9+ years of experience in digital design, with a focus on RTL design for complex SoCs
Deep expertise in Verilog/SystemVerilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Experience with synthesis, static timing analysis, and DFT concepts
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Proven track record of leading technical teams and delivering successful silicon
Excellent analytical, problem-solving, and communication skills
Passion for innovation and delivering high-quality, scalable solutions

Job Responsibility

Define and review SoC architecture and design specifications
Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
Contribute to IP selection, evaluation, and integration in SoC designs
Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels

Fulltime

Principal Physical verification engineer

Sandisk

Location:
India , Hyderabad

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
February 23, 2026

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Principal Engineer, ASIC Development Engineering (RTL Design)

Principal Physical verification engineer

Sandisk

Location:India , Hyderabad

Category:IT - Software Development

Contract Type:Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:February 23, 2026

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Location:
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Category:
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Contract Type:
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Job Posted:
February 23, 2026