Principal Physical verification engineer Job at Sandisk (Hyderabad)

Principal Engineer Physical Design

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

Malaysia , Gelugor

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

BS/BE/BTech/MS/ME/MTech in Electronics or Microelectronics/VLSI, or Electrical Engineering
Min 15+ years of experience in semiconductor design
Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams
Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, EMIR closure and physical verification
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of complex partitions/subsytems through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification
Own complete PD execution of Sub-systems/Sub-chips instantiating/integrating multiple other physical partitions
Implement robust clock distribution solutions using appropriate methods that meet design requirements
Have close collaboration with RTL team (RTL2PD liaison) to help drive and resolve design issues related to block closure
Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach
Make independent and good technical trade-off decisions between power, area, and timing (PPA)
Lead, guide and coordinate with all sub-partitions PD owners to be able to take Subsystem/Subchip through PD (construction through signoff) closure
Collaborating and influencing various aspects of PD Methodology will also be key requirement in this role
Additionally drive key pieces of PD implementation methodology or specific areas such as Clocking/Low power optimization/Power & Performance methodology
Partner closely with PD flow/CAD team and PD methodology team

Fulltime

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Lead the PnR convergence recipe development for designs at blocks/subsystem and subchip level
Develop and implement methodologies and strategies to improve physical design efficiency and performance
Develop and implement methodologies and strategies to sign off blocks, subsystem/Subchip in the areas of static timing, physical verification, functional logics equivalence, low power verification and electromigration and IR drop
Implementation of functional ECO with least physical design impact
Design and implement the global clocking scheme at SOC and sub chip levels
Stay current with industry trends and emerging technologies to continuously improve physical design processes and methodologies
Installation and quality check of internal and external IP collaterals for use by Physical Design execution team
Conduct physical design reviews, identify and resolve design issues, and provide guidance to junior engineers

Fulltime

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

India , Bangalore

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Bachelor's or master’s in electrical or computer engineering or related field with 12+ years of experience
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeouts of complex ASICs in leading edge technology
Experience in leading team to deliver planned PD goals
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter

Job Responsibility

Physical Design tasks at block, subsystem, sub-chip, and/or full-chip level
Floorplanning, Synthesis, Placement, CTS and custom clocking, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM
Physical Design flow development/automation and evaluation of and recommendations for technology, IP, and vendor selection
Drive PD team at block/Sub System / Sub Chip / SOC level to set and deliver quality results as per planned milestone goals
Work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team

Fulltime

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeouts of complex ASICs in leading edge technology
Experience in leading team to deliver planned PD goals

Job Responsibility

Lead and execute Physical Design activities at block, sub-chip, and full-chip levels
Contribute to Physical Design flow development, automation, and methodology improvements
Evaluate and recommend technology nodes, IP selection, EDA tools, and vendor solutions
Provide clear and concise status updates on progress, risks, and mitigation plans to management
Operate independently with minimal supervision while maintaining strong attention to detail
Support program needs, including occasional travel as required
Drive all phases of implementation including: Floorplanning
Synthesis
Placement and optimization
Clock Tree Synthesis (CTS) and custom clocking

Fulltime

Principal Quantum Design Verification Engineer

At Microsoft Quantum, we aim to empower science and scientists to solve the worl...

Location

United States , Redmond

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment
OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check
Citizenship & Citizenship Verification
Ability to leverage AI tools to drive innovation and efficiency
Ability to work in an 'AI-first' environment using modern AI tools to accelerate discovery through hardware development

Job Responsibility

Own verification environments and tests for IP and SoC designs, and validate designs in simulation with both pre- and post-layout Register-Transfer Level (RTL) and netlists
Coordinate the execution of contingent staff and external vendors to ensure verification deliverables meet specification and schedule
Set up and manage databases and flows for SoC and IP repositories
set up bug-tracking systems and log, track, manage, and close bugs and issues
drive milestone reviews and status reports
Create test plans for pre-silicon simulation verification across both digital and analog components, including the development of Analog Mixed-Signal (AMS) simulation models
Collaborate with the Design For Test (DFT) team to test DFT features
Align verification methodologies with wider teams and drive continuous improvement to Design Verification processes for at-scale execution
Collaborate effectively with architects, analog mixed-signal designers, verification engineers, and physical design, DFT, and other front-end design teams
Embody our culture and values

Fulltime

Asic / Physical Design Engineer (Int, Senior and Principal)

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

8+ years in ASIC Physical Design / Backend Implementation (PnR)
End-to-end experience from netlist to GDSII (full physical design flow)
Strong hands-on with Place & Route (floorplan, CTS, routing, optimization)
Proven timing closure expertise (setup/hold, ECO implementation)
Deep experience with Synopsys and/or Cadence tool suites
Advanced node exposure (FinFET, sub-10nm / 7nm / 5nm preferred)
Strong Static Timing Analysis (STA) and timing report analysis
Experience with clock tree synthesis (CTS) and clock optimization
Solid understanding of DRC/LVS and physical verification flows
IR drop / power integrity analysis and optimization experience

Fulltime

Model Based Systems Engineer Principal

Be part of a fast-paced, high energy, team supporting the Resilient Missile Warn...

Location

United States , Colorado Springs

Salary:

128317.13 - 308344.14 USD / Year

Arcfield

Expiration Date

Until further notice

Requirements

BS 10-12 years, MS 8-10 years, PhD 5-7 years
BS or higher in engineering, physics, programming or related technical degree
Must possess and maintain a secret clearance and be able to successfully crossover with the supported client
Demonstrated knowledge and practical application of UML / SysML modeling languages and experience applying this common structure to an MBSE solution.
Demonstrated proficiency in using Cameo or other UML based Architecture modeling tools.
Knowledge of standard DoDAF architectural frameworks to include UPDM and/or UAF.
Experience with systems engineering processes in support of system life cycle development.
Basic knowledge of architecture, requirements engineering, CONOPS development, verification, test and system integration to accommodate End to End Systems Engineering.
Experience in MBSE implementation ranging from conceptual to physical implementations
including Data Modeling, Data Ingest, and model query.

Job Responsibility

Assess engineering artifacts and develop models of mission systems using a MBSE tool suite that includes DOORS Next, Cameo and other COTS tools.
Apply systems engineering modeling methodologies to develop mission models.
Define and demonstrate the appropriate data standards, data structures, and supporting COTS, GOTS, and Open-Source technologies required to manage the data needs.
Integrate enterprise tools and develop MBSE-based processes to support requirements engineering, the customer's ERB process, CONOPS and architecture development, Risk, Issues and Opportunity Management boards, schedule management, test and verification strategy development, and system integration of new initiatives in support of expanded mission capabilities.
Facilitate collaborative meetings between the MBSE users and the tool development team to communicate modeling needs and help innovate potential solutions.
Provides technical advice and guidance to senior managers regarding the creation and implementation of new MBSE methods and techniques.

What we offer

Health Insurance
Life Insurance
Paid Time Off
Holiday Pay
Short Term and Long-Term Disability
Retirement and Savings
Learning and Development opportunities
wellness programs as well as other optional benefit elections.

Fulltime

Principal Engineer, ASIC Development Engineering (PD Methodology & CAD Flow)

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...

Location

India , Hyderabad

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

8+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs
Deep, hands-on understanding of complete PD flow, including: Synthesis, Logical Equivalence Checking (LEC), DFT insertion and integration, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis
Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA
Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes
M.Tech in VLSI Design or a related field (or equivalent industry experience)
Proficiency in scripting and automation using TCL, Perl, and/or Python
Experience working in multi-project, high-complexity environments with tight schedules

Job Responsibility

Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices
Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions
Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence
Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules
Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability
Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity
Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges

Fulltime

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Principal Physical verification engineer

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