CrawlJobs Logo

Principal Physical Design Engineer

India, Bangalore · Job Posted March 19, 2026
Apply Position
Job Link Share

Job Description

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the SCHIE team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Physical Design Engineer to join the team.

Job Responsibility

  • Physical Design tasks at block, subsystem, sub-chip, and/or full-chip level
  • Floorplanning, Synthesis, Placement, CTS and custom clocking, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM
  • Physical Design flow development/automation and evaluation of and recommendations for technology, IP, and vendor selection
  • Drive PD team at block/Sub System / Sub Chip / SOC level to set and deliver quality results as per planned milestone goals
  • Work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team

Requirements

  • Bachelor's or master’s in electrical or computer engineering or related field with 12+ years of experience
  • Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
  • Experience in tapeouts of complex ASICs in leading edge technology
  • Experience in leading team to deliver planned PD goals
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
  • These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter

Looking for more opportunities?

Search for other job offers that match your skills and interests.

Similar Jobs for

Principal Physical Design Engineer

8 matching positions

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Mountain View
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Job Responsibility
Job Responsibility
  • Lead the PnR convergence recipe development for designs at blocks/subsystem and subchip level
  • Develop and implement methodologies and strategies to improve physical design efficiency and performance
  • Develop and implement methodologies and strategies to sign off blocks, subsystem/Subchip in the areas of static timing, physical verification, functional logics equivalence, low power verification and electromigration and IR drop
  • Implementation of functional ECO with least physical design impact
  • Design and implement the global clocking scheme at SOC and sub chip levels
  • Stay current with industry trends and emerging technologies to continuously improve physical design processes and methodologies
  • Installation and quality check of internal and external IP collaterals for use by Physical Design execution team
  • Conduct physical design reviews, identify and resolve design issues, and provide guidance to junior engineers
  • Fulltime
Read More
Arrow Right

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Mountain View
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
  • Experience in tapeouts of complex ASICs in leading edge technology
  • Experience in leading team to deliver planned PD goals
Job Responsibility
Job Responsibility
  • Lead and execute Physical Design activities at block, sub-chip, and full-chip levels
  • Contribute to Physical Design flow development, automation, and methodology improvements
  • Evaluate and recommend technology nodes, IP selection, EDA tools, and vendor solutions
  • Provide clear and concise status updates on progress, risks, and mitigation plans to management
  • Operate independently with minimal supervision while maintaining strong attention to detail
  • Support program needs, including occasional travel as required
  • Drive all phases of implementation including: Floorplanning
  • Synthesis
  • Placement and optimization
  • Clock Tree Synthesis (CTS) and custom clocking
  • Fulltime
Read More
Arrow Right

Principal Engineer Physical Design

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
Malaysia , Gelugor
Salary
Salary:
Not provided
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BS/BE/BTech/MS/ME/MTech in Electronics or Microelectronics/VLSI, or Electrical Engineering
  • Min 15+ years of experience in semiconductor design
  • Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams
  • Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, EMIR closure and physical verification
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
  • This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Job Responsibility
Job Responsibility
  • Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of complex partitions/subsytems through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification
  • Own complete PD execution of Sub-systems/Sub-chips instantiating/integrating multiple other physical partitions
  • Implement robust clock distribution solutions using appropriate methods that meet design requirements
  • Have close collaboration with RTL team (RTL2PD liaison) to help drive and resolve design issues related to block closure
  • Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach
  • Make independent and good technical trade-off decisions between power, area, and timing (PPA)
  • Lead, guide and coordinate with all sub-partitions PD owners to be able to take Subsystem/Subchip through PD (construction through signoff) closure
  • Collaborating and influencing various aspects of PD Methodology will also be key requirement in this role
  • Additionally drive key pieces of PD implementation methodology or specific areas such as Clocking/Low power optimization/Power & Performance methodology
  • Partner closely with PD flow/CAD team and PD methodology team
  • Fulltime
Read More
Arrow Right

Asic / Physical Design Engineer (Int, Senior and Principal)

Location
Location
Canada , Ottawa
Salary
Salary:
Not provided
myticas.com Logo
Myticas Consulting
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 8+ years in ASIC Physical Design / Backend Implementation (PnR)
  • End-to-end experience from netlist to GDSII (full physical design flow)
  • Strong hands-on with Place & Route (floorplan, CTS, routing, optimization)
  • Proven timing closure expertise (setup/hold, ECO implementation)
  • Deep experience with Synopsys and/or Cadence tool suites
  • Advanced node exposure (FinFET, sub-10nm / 7nm / 5nm preferred)
  • Strong Static Timing Analysis (STA) and timing report analysis
  • Experience with clock tree synthesis (CTS) and clock optimization
  • Solid understanding of DRC/LVS and physical verification flows
  • IR drop / power integrity analysis and optimization experience
  • Fulltime
Read More
Arrow Right

Principal Engineer - Physical Security Innovation

In alignment with our Microsoft values, we are committed to cultivating an inclu...
Location
Location
Ireland , Dublin
Salary
Salary:
Not provided
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Master's Degree in Statistics, Mathematics, Computer Science, Risk Management, Cyber Security, or related field AND several years of experience in physical security design, engineering, construction and technical operation, threat modeling
  • OR Bachelor's Degree in Statistics, Mathematics, Computer Science, Risk Management, Cyber Security, or related field AND several years of experience in physical security design, engineering, construction and technical OR equivalent experience.
  • Several years of experience with physical security systems and programs.
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
  • This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
Job Responsibility
Job Responsibility
  • Physical Security Innovation: Drives the strategy for introducing new security concepts and technologies into an existing, global, and expansive datacenter portfolio.
  • Customer/Partner Results: Helps to make connections and assist in developing agreements among groups to clarify priorities, dependencies, and provide coordination across groups.
  • Planning and Research: Influences product schedules, dependencies and risk assessments as part of security design and analysis.
  • Security Issues Analysis: Defines the strategic vision and leads execution of roadmap for security initiatives.
  • Security Reviews and Reporting: Leads large-scale security and architectural design reviews for feature areas.
  • Solution Engineering and Mitigation: Identifies, prioritizes, and targets complex security issues that cause significant negative impact to customers.
  • Subject Matter Expertise: Helps others by sharing expertise to identify potential security issues, tools, mitigations, and processes.
  • Fulltime
Read More
Arrow Right

ASIC Principal Design Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Strong Verilog RTL coding skills
  • Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
  • Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
  • Knowledge of high performance memory subsystems
  • Knowledge of multi-domain clock synchronization and high-speed serial interfaces
  • Strong problem solving and ASIC debugging skills
  • Excellent written and verbal communications skills
  • MSEE or BSEE is required with 8 plus years of experience
Job Responsibility
Job Responsibility
  • Define and architect high-performance blocks for the latest, most advanced networking ASICs
  • Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
  • Collaborate with the verification team in the development of the testplan and assist in debugging test failures
  • Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
What we offer
What we offer
  • Health & Wellbeing
  • Personal & Professional Development
  • Unconditional Inclusion
Read More
Arrow Right

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's or master’s in electrical or computer engineering or related field with 15+ years of experience
  • Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
  • Experience in tapeouts of complex ASICs in leading edge technology
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Job Responsibility
Job Responsibility
  • Lead a team in defining implementation and execution plan for a schip/SOC
  • Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
  • Drive the to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
  • Optimizing technology, libraries, physical design, RTL design, and architecture
  • Leading the team in defining the implementation and execution plan for a subchip/SOC
  • Collaborating with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects to ensure a cohesive plan
  • Executing the defined plan to ensure successful tapeout of the subchip/SOC
  • Driving the team to achieve the best performance, power, and area (PPA) for AI system-on-chips
  • Optimizing technology choices, libraries, physical design methodologies, RTL design strategies, and architectural decisions to meet performance targets
  • Ensuring that the physical design aspects align with the overall project goals and timelines
  • Fulltime
Read More
Arrow Right

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Raleigh
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • Ability to provide proof of country of citizenship or proof of US residency or other protected status for export control assessment
  • Bachelor's or master’s in electrical or computer engineering or related field with 10+ years of experience
  • Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
  • Experience in tapeout of complex ASICs in leading edge process node technology
  • 8+ years of hands-on experience in EDA vendor tools such as Fusion Compiler, VCLP, Primetime, Formality, or Cadence Innovus and Conformal
Job Responsibility
Job Responsibility
  • Lead a team in defining implementation and execution plan for a schip/SOC
  • Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
  • Drive the team to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
  • Optimizing technology, libraries, physical design, RTL design, and architecture
  • Collaborate with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects
  • Provide technical guidance and mentorship to team members
  • Oversee the development and implementation of physical design flows and methodologies
  • Collaborate with cross-functional teams to address design challenges and optimize for manufacturability
  • Monitor progress, identify risks, and implement mitigation strategies
  • Keep abreast of the latest industry trends, tools, and techniques in physical design
  • Fulltime
Read More
Arrow Right