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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
Job Responsibility:
Lead and execute Physical Design activities at block, sub-chip, and full-chip levels
Contribute to Physical Design flow development, automation, and methodology improvements
Evaluate and recommend technology nodes, IP selection, EDA tools, and vendor solutions
Provide clear and concise status updates on progress, risks, and mitigation plans to management
Operate independently with minimal supervision while maintaining strong attention to detail
Support program needs, including occasional travel as required
Drive all phases of implementation including: Floorplanning
Synthesis
Placement and optimization
Clock Tree Synthesis (CTS) and custom clocking
Routing
Static Timing Analysis (STA)
Physical Verification
Formal Equivalency
Power optimization and efficiency analysis
IR-drop and Electromigration (EM) analysis
Requirements:
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeouts of complex ASICs in leading edge technology
Experience in leading team to deliver planned PD goals