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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Compute Silicon & Manufacturing Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Memory Controller RTL Design Engineer to join the team.
Job Responsibility:
Define and implement the micro-architectural specification in Verilog or System Verilog
Refine your implementation for area, power and performance
Integration of the functional IP into SoC
Exercise the functionality of the block by writing basic tests
Perform design quality checks such as Lint, CDC/RDC, Low Power Intent, timing QoR
Automate tasks using scripting and AI for efficiency
Collaborate with highly energetic cross functional team members with respect and with One Microsoft mentality to establish synergies
Collaborate with IP providers
Deliver high quality functional blocks on schedule and with professional integrity
Challenge the status quo with your growth mindset
Requirements:
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Nice to have:
10 or more years designing and implementing novel high-performance DDR4 or DDR5 memory controllers
Background and understanding of Digital Design principles as part of SoC and/or IP development teams
Applied understanding of low power design principles
Highly Proficient in Verilog/System Verilog coding constructs
Highly Proficient in high-speed design principles
Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
Familiarity with Synthesis and STA tools
Ability to write scripts using Perl, Tcl, Python etc
Experience with multi-bit error correction such as Reed-Solomon Encoding
Understanding of Industry standard interface protocols such as CHI, APB, AMBA