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Microsoft Corporation Logo Microsoft Corporation · IT - Software Development

Principal Logic Design Engineer

United States, Raleigh 139900.00 - 274800.00 USD / Year · Job Posted January 30, 2026
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Job Description

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the AI Silicon Engineering (AISiE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Logic Design Engineer to join the team.

Job Responsibility

  • Establish yourself as an integral member of a digital logic design team for the development of AI components with focus on micro-architectural based functions and features
  • Be responsible for the logic design/Register Transfer Level (RTL) entry, design quality including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc., and timing closure of high-performance digital IP
  • Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent
  • Interface with physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design
  • Provide technical leadership through mentorship and strong teamwork

Requirements

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Nice to have

  • 8+ years expertise in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure
  • 7+ years of experience in synthesis, timing constraints, power / performance / area (PPA) trade-offs and post-silicon debug
  • 10+ years of experience in one or more of the following – floating point arithmetic and datapath design, DMA design, subsystem designs/integration, or custom logic design
  • 5+ years of experience leading logic design teams
  • Multiple successful ASIC tape outs in deep sub-micron technologies
  • Experience with scripting languages such as Python or Perl
  • Experience debugging designs as well as simulation environment
  • Knowledge of verification principles, testbenches, UVM, and coverage
  • Experience working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs
  • Working knowledge of writing assertions, coverage and formal verification
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