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Hewlett Packard Enterprise Logo Hewlett Packard Enterprise · IT - Software Development

Principal Hardware Design Engineer

India, Bengaluru · Job Posted June 28, 2026
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Job Description

We are seeking Principal Hardware Design Engineer (TCP05) to provide technical leadership and architectural ownership across critical hardware subsystems for next‑generation networking products. This role is intended for deeply experienced engineers who operate as technical authorities, drive system‑level architecture, resolve the most complex system‑level challenges, and elevate the quality and consistency of hardware designs across products. You will influence multi‑team technical decisions while remaining hands‑on where it matters most.

Job Responsibility

  • Define hardware architecture for complex boards and critical subsystems working with senior architects
  • Lead system‑level HW design strategy, addressing: High‑speed interconnect architecture, Signal integrity and channel strategy, Power architecture, sequencing, and margins, Reliability, lifecycle, and scale considerations
  • Drive technical decision‑making across teams, aligning hardware, SI/PI, firmware, software, mechanical, thermal, and manufacturing requirements
  • Serve as a technical authority for high‑risk or ambiguous hardware issues, leading root‑cause analysis and resolution of complex system‑level failures
  • Influence product feasibility, cost structure (COGS), performance, and quality through early trade‑off analysis and architectural guidance
  • Set and evolve hardware design standards, best practices, and methodologies to improve design reuse, robustness, and time‑to‑market
  • Review and guide designs led by Senior and Experienced engineers, ensuring architectural alignment and technical rigor
  • Mentor/guide team engineers, helping them grow into technical leaders

Requirements

  • Bachelor’s or Master’s degree in Electronics / Electrical Engineering or a closely related discipline
  • 16+ years of experience in high‑performance hardware and system‑level design, including multiple products shipped to high‑volume production
  • Demonstrated ownership of system or subsystem level architecture within complex networking or compute platforms
  • Deep expertise in high‑speed digital design, including: Signal integrity at scale, SerDes architecture and channel budgeting, NRZ and PAM4 design considerations
  • Strong command of power architecture, including PDN design, sequencing, regulation strategies, and margin analysis
  • Extensive experience with networking hardware platforms, such as switches, routers, or high‑performance network appliances
  • Strong familiarity with interfaces and technologies including: DDR4 / DDR5, PCIe (Gen4 / Gen5 or beyond), Ethernet PHYs and MACs (1G → 100G+), SGMII, XAUI, and high‑speed SerDes links
  • Working knowledge of PoE architectures, CPU subsystems (ARM, Intel x86, AMD x86), and board‑level system integration
  • Proficiency with Cadence PCB tools (OrCAD / Allegro) and strong ability to review and guide complex designs
  • Proven ability to lead system‑level debug using advanced lab instrumentation: High‑bandwidth oscilloscopes and TDRs, BERTs, DCA, protocol analyzers, JTAG and system debug tools
  • Expertise in driving data‑based decisions from characterization and empirical analysis
  • Strong technical judgment and ability to make long‑term architectural trade‑offs
  • Clear and persuasive communication skills
  • able to: Present architectural proposals, Defend design decisions with data, Influence decision making of senior technical stakeholders and executives
  • Comfortable operating across organizational boundaries and multi‑site teams
  • Passion for mentoring and raising the technical bar across the organization

What we offer

  • Health & Wellbeing
  • Personal & Professional Development
  • Unconditional Inclusion
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