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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Silicon and Manufacturing team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a seasoned architect with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
Job Responsibility
Architecting and developing PCIe Gen 7 subsystem
Working with Vendors evaluate IP and make recommendations
Working with Performance Modeling team to analyze SOC/platform Azure IO workloads
Working closely with Strategic Planning and Architecture as well as internal customers to understand workload and use case requirements with specific focus on identifying full stack optimization opportunities within the context of the overall memory hierarchy
Collaborating across teams to come up with the best solution possible with a One Microsoft mindset
Challenging the status quo with a growth mindset to push the envelope and enable world-class SOC products across Microsoft
Principal PCIe Architect responsible for defining next-generation PCIe/CXL architecture for Microsoft Azure silicon platforms, delivering high-performance, scalable, and reliable I/O subsystems
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US residency or other protected status
the successful candidate's citizenship will be verified with a valid passport
Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable
Nice to have
10+ years of experience in SoC or I/O architecture
Deep expertise in PCIe architecture (Gen4/Gen5/Gen6 or later)
Understanding of SoC/system architecture and integration
Experience delivering PCIe-based subsystems from architecture to silicon production
Experience working with cross-functional teams (design, DV, firmware, system software)
Experience with PCIe Gen5/Gen6/Gen7 and emerging standards
Experience with CXL architecture and memory/coherency models
Knowledge of I/O virtualization and system-level interactions (IOMMU, SR-IOV, ATS)
Experience with performance modeling/analysis for hyperscale workloads
Experience with RAS, power management, and security architecture in I/O subsystems
Experience in post-silicon validation, debug, and deployment
Proven leadership in driving architecture across multiple programs