Principal FPGA / RTL Design Engineer Job at Silvus Technologies (International) (Irvine)

Principal FPGA / RTL Design Engineer - Signal Processing

Participate in all aspects of the research and development process from concept ...

Location

United States , Los Angeles

Salary:

165000.00 - 250000.00 USD / Year

Silvus Technologies (International)

Expiration Date

Until further notice

Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields
Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs
Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Must be U.S. Person (U.S. Citizen, or Permanent Resident) due to clients under U.S. federal contracts
All employment is contingent upon the successful clearance of a background check

Job Responsibility

Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering Teams

Fulltime

Principal FPGA / RTL Design Engineer - Signal Processing

Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who ...

Location

United States , Irvine

Salary:

165000.00 - 250000.00 USD / Year

Silvus Technologies (International)

Expiration Date

Until further notice

Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields
Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs
Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Must be a U.S. Citizen due to clients under U.S. government contracts
All employment is contingent upon the successful clearance of a background check

Job Responsibility

Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering teams

Fulltime

Senior FPGA Architect / Principal FPGA Engineer

Senior FPGA Architect / Principal FPGA Engineer – Real-Time Processing Systems

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

Architect-level FPGA expertise designing high-performance real-time processing systems and complex programmable logic architectures
Advanced RTL development using Verilog / SystemVerilog for high-throughput pipelines, accelerators, and timing-sensitive hardware logic
Experience building FPGA-based SoC architectures including AXI/Avalon fabrics, DMA engines, memory controllers, and multi-clock domain designs
Strong background in high-bandwidth data-path design, resource utilization optimization, timing feasibility, and device architecture trade-offs
Hands-on expertise with Xilinx UltraScale+/MPSoC and/or Intel FPGA families (Arria, Stratix, Agilex) and associated development toolchains
Deep experience integrating high-speed interfaces such as PCIe, Ethernet, and high-speed serial transceivers (SERDES)
Familiarity with video/media transport or other latency-sensitive real-time processing environments involving high data throughput
Proven ability to drive timing closure, synthesis, floorplanning, constraint management, and place-and-route optimization
Strong verification leadership including simulation-driven validation, UVM environments, constrained-random testing, and coverage-driven methodologies
Practical lab experience performing FPGA bring-up, system integration, and hardware debug using scopes, logic analyzers, and embedded debug tools

Fulltime

New

Principal FPGA Design Engineer - 4G/5G Radio Systems

Are you a FPGA Design Engineer looking for a new opportunity? Are you looking fo...

Location

Canada , Kanata

Salary:

62.19 - 72.43 USD / Hour

Randstad

Expiration Date

June 29, 2026

Requirements

7+ Years of RTL Expertise: Proven track record in high-complexity FPGA design, specifically using SystemVerilog or Verilog. (Note: Candidate must be willing to work exclusively in a non-VHDL environment).
Altera/Intel Toolchain: Mastery of Quartus Prime for synthesis, place-and-route, and timing closure on high-density FPGAs.
DSP Modeling: Proficiency in MATLAB and Simulink for algorithmic modeling and fixed-point simulation prior to RTL implementation.
Protocol Mastery: Deep expertise in AXI (AXI4-Stream, AXI4-Lite) and Ethernet (10G/25G/100G) protocol implementation.
High Speed Interfaces: Practical experience with JESD204B/C, PCIe, and multi-gigabit SERDES transceivers.
Synchronization: Understanding of timing and synchronization protocols, such as PTP (IEEE 1588) and SyncE.
Wireless Infrastructure: Direct experience developing Radio Units (RU) or Massive MIMO systems.
Industry Standards: Functional knowledge of 3GPP physical layer specifications and O-RAN (Open RAN) Fronthaul interfaces (eCPRI/CPRI).
Signal Processing: Experience implementing Digital Up/Down Conversion (DUC/DDC), Crest Factor Reduction (CFR), or Digital Pre-Distortion (DPD) in hardware.
Advanced Verification: Experience with UVM (Universal Verification Methodology) and constrained-random testing to ensure 'first-time-right' silicon/FPGA bitstreams.

Job Responsibility

Define System Requirements: Translate high-level customer needs and 3GPP/O-RAN standards into detailed functional specifications for the entire FPGA ecosystem.
Drive 5G Roadmap: Architect FPGA IP specifically for 4G/5G Radio Units, ensuring designs align with industry trends and long-term organizational strategy.
Strategic Design Choices: Set the standard for product excellence by selecting optimal components and design methodologies to meet aggressive cost and performance targets.
High-Complexity RTL Development: Lead the implementation of complex logic blocks using SystemVerilog, focusing on high-speed Ethernet and AXI protocol integration.
Model-Based Design: Utilize MATLAB and Simulink to model signal processing algorithms before translating them into hardware-efficient RTL.
Ensure Design Integrity: Oversee the full validation lifecycle, from UVM-based simulation to hands-on system-level testing and timing closure using Altera Quartus.
Hardware-Software Synergy: Partner closely with software and RF teams to ensure seamless interoperability between hardware logic and low-level software drivers.
Technical Authority: Act as the primary consultant on critical, high-impact projects, providing 'whiteboard-level' solutions to unusually complex engineering hurdles.
Team Mentorship: Provide technical guidance to junior engineers, fostering a culture of best practices in RTL coding and version control (Git).
Executive Communication: Bridge the gap between engineering and management by communicating project progress, risks, and technical visions to senior leadership.

Fulltime

Principal Quantum Systems Digital Design Engineer

Microsoft is the world’s center of expertise on topological quantum computing. W...

Location

United States , Redmond

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Electrical/Computer Engineering, or related field AND 3+ years experience in industry or in a research and development environment
OR Master's Degree in Physics, Electrical/Computer Engineering, or related field AND 4+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Electrical/Computer Engineering, or related field AND 6+ years experience in industry or in a research and development environment
OR equivalent experience
6+ years programming experience in related programming languages
6+ years experience in a collaborative environment
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
Ability to work in an "AI first" environment using modern AI tools to accelerate discovery through hardware development
Familiarity with designing and building AI agents/copilots that assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval

Job Responsibility

Design & implement RTL for streaming, low‑latency pipelines (e.g., readout classifiers, syndrome aggregation, and QEC decoder kernels) in Verilog/SystemVerilog, including resource/performance trade‑offs and power/thermal considerations
Design and implement high‑speed interconnects between subsystems (AXI4/AXI‑Stream, JESD204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring‑up, and throughput/latency tuning
Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi‑domain timing closure, async FIFOs, metastability analysis) for deterministic performance
Co‑design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams
contribute to system‑level design reviews
Verification and validation: develop simulation and constrained‑random tests (SV/UVM or equivalent), build on‑board diagnostics (ILA/ChipScope), and execute lab bring‑up with scopes, VNAs, LA/SC, and RF instruments
Tool flow & CI: own synthesis/implementation (Vivado/Vitis or Quartus/Prime), timing sign‑off, and reproducible, scripted builds (Tcl/Python) integrated with Git/Azure DevOps CI/CD
Quality & documentation: produce clear design docs, interface specs, and bring‑up guides
participate in rigorous code/design reviews and post‑silicon/post‑fabrication retros

Fulltime

New

Business Support Specialist

We are recruiting dedicated and driven individuals to join our Corporate Busines...

Location

United Kingdom , Aylesbury

Salary:

32740.00 - 34292.00 GBP / Year

Buckinghamshire Council

Expiration Date

May 20, 2026

Requirements

Efficient and highly organised
Excellent written and oral communication skills as well as excellent interpersonal skills
Excellent IT skills
Ability to establish good working relationships
Ability to interact with internal colleagues including senior management and external partners to build effective relationships
Ability to deal with people at all levels confidently, sensitively and diplomatically
Ability to be discrete and handle confidential information appropriately
Ability to research and assemble information and prepare draft briefing papers / correspondence
Ability to collate and organise data / information efficiently

Job Responsibility

Plan, organise and deliver your workload to ensure information and business support is completed on time and to required standards
Provide specialist administrative advice and support to customers, ensuring needs are understood and responded to appropriately
Collate, organise and process information and documentation to support service delivery
Produce documents, reports and correspondence accurately and to required timescales
Arrange and coordinate meetings, manage diaries, support events and take minutes where needed
Support financial processes, including raising and processing purchase orders, invoices and other transactions
Liaise with colleagues, managers and external contacts to resolve queries and maintain smooth workflow
Identify opportunities to improve processes and contribute to efficient, high‑quality service delivery

What we offer

discounts at various cafes, restaurants, and shops
auto-enrolment in our generous pension scheme
membership to Costco
discounted gym memberships
travel discounts with Arriva
health and well-being initiatives including an Employee Assistance Programme, Mental Health First Aiders and mindfulness workshops
Employee Representative Group
ongoing support
opportunities to take part in fun activities such as fundraising and social events

Parttime

!

New

Server/Waitstaff

What you will do as a Server - Set and clear tables, take residents’ dining orde...

Location

United States , Irvine

Salary:

16.90 - 20.28 USD / Hour

Atria Senior Living

Expiration Date

Until further notice

Requirements

No experience needed
On-the-job training – get paid to get trained!

Job Responsibility

Set and clear tables, take residents’ dining orders and provide the highest level of customer service
Review menus with residents and acquaint new residents with dining at Atria
Assist with the preparation, delivery and cleanup of daily meals, banquets and special events
Create a strong sense of teamwork with your colleagues and positive relationships with residents
Clean and sanitize carpet, tables, chairs, condiment containers and equipment used in the dining room

What we offer

Competitive Pay
Paid Holidays & PTO
Comprehensive Health Plans
Career Advancement Opportunities
Tuition Reimbursement
Employee Loyalty Rewards Program
Retirement Savings Plan with Employer Match
Rewards & Recognition
Health & Safety

Parttime

New

Certified Nursing Assistant (CNA)

NOW HIRING: Certified Nursing Assistants (CNAs) Complete Care at Phillipsburg, ...

Location

United States , Phillipsburg

Salary:

20.50 - 23.90 USD / Hour

Complete Care at Phillipsburg

Expiration Date

Until further notice

Requirements

Active NJ CNA Certification
A caring heart + strong team spirit

Job Responsibility

Assist residents with daily living activities (ADLs)
Keep residents safe, comfortable & cared for
Be a vital member of our compassionate care team

What we offer

Competitive Pay + Shift Differentials
Access your pay when YOU need it!
Full Benefits, PTO & Paid Holidays
Tuition Reimbursement + Career Growth

Principal FPGA / RTL Design Engineer

Silvus Technologies (International)

Location:
United States , Irvine

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
December 12, 2025

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