Principal FPGA / RTL Design Engineer Job at Silvus Technologies (International) (Irvine)

Principal FPGA / RTL Design Engineer - Signal Processing

Participate in all aspects of the research and development process from concept ...

Location

United States , Los Angeles

Salary:

165000.00 - 250000.00 USD / Year

Silvus Technologies (International)

Expiration Date

Until further notice

Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields
Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs
Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Must be U.S. Person (U.S. Citizen, or Permanent Resident) due to clients under U.S. federal contracts
All employment is contingent upon the successful clearance of a background check

Job Responsibility

Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering Teams

Fulltime

Principal FPGA / RTL Design Engineer - Signal Processing

Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who ...

Location

United States , Irvine

Salary:

165000.00 - 250000.00 USD / Year

Silvus Technologies (International)

Expiration Date

Until further notice

Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields
Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs
Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
Must be a U.S. Citizen due to clients under U.S. government contracts
All employment is contingent upon the successful clearance of a background check

Job Responsibility

Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting
familiarity with logic analyzers
Provide support to the RF and Software Engineering teams

Fulltime

Senior FPGA Architect / Principal FPGA Engineer

Senior FPGA Architect / Principal FPGA Engineer – Real-Time Processing Systems

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

Architect-level FPGA expertise designing high-performance real-time processing systems and complex programmable logic architectures
Advanced RTL development using Verilog / SystemVerilog for high-throughput pipelines, accelerators, and timing-sensitive hardware logic
Experience building FPGA-based SoC architectures including AXI/Avalon fabrics, DMA engines, memory controllers, and multi-clock domain designs
Strong background in high-bandwidth data-path design, resource utilization optimization, timing feasibility, and device architecture trade-offs
Hands-on expertise with Xilinx UltraScale+/MPSoC and/or Intel FPGA families (Arria, Stratix, Agilex) and associated development toolchains
Deep experience integrating high-speed interfaces such as PCIe, Ethernet, and high-speed serial transceivers (SERDES)
Familiarity with video/media transport or other latency-sensitive real-time processing environments involving high data throughput
Proven ability to drive timing closure, synthesis, floorplanning, constraint management, and place-and-route optimization
Strong verification leadership including simulation-driven validation, UVM environments, constrained-random testing, and coverage-driven methodologies
Practical lab experience performing FPGA bring-up, system integration, and hardware debug using scopes, logic analyzers, and embedded debug tools

Fulltime

New

Principal FPGA Design Engineer - 4G/5G Radio Systems

Are you a FPGA Design Engineer looking for a new opportunity? Are you looking fo...

Location

Canada , Kanata

Salary:

62.19 - 72.43 USD / Hour

Randstad

Expiration Date

June 29, 2026

Requirements

7+ Years of RTL Expertise: Proven track record in high-complexity FPGA design, specifically using SystemVerilog or Verilog. (Note: Candidate must be willing to work exclusively in a non-VHDL environment).
Altera/Intel Toolchain: Mastery of Quartus Prime for synthesis, place-and-route, and timing closure on high-density FPGAs.
DSP Modeling: Proficiency in MATLAB and Simulink for algorithmic modeling and fixed-point simulation prior to RTL implementation.
Protocol Mastery: Deep expertise in AXI (AXI4-Stream, AXI4-Lite) and Ethernet (10G/25G/100G) protocol implementation.
High Speed Interfaces: Practical experience with JESD204B/C, PCIe, and multi-gigabit SERDES transceivers.
Synchronization: Understanding of timing and synchronization protocols, such as PTP (IEEE 1588) and SyncE.
Wireless Infrastructure: Direct experience developing Radio Units (RU) or Massive MIMO systems.
Industry Standards: Functional knowledge of 3GPP physical layer specifications and O-RAN (Open RAN) Fronthaul interfaces (eCPRI/CPRI).
Signal Processing: Experience implementing Digital Up/Down Conversion (DUC/DDC), Crest Factor Reduction (CFR), or Digital Pre-Distortion (DPD) in hardware.
Advanced Verification: Experience with UVM (Universal Verification Methodology) and constrained-random testing to ensure 'first-time-right' silicon/FPGA bitstreams.

Job Responsibility

Define System Requirements: Translate high-level customer needs and 3GPP/O-RAN standards into detailed functional specifications for the entire FPGA ecosystem.
Drive 5G Roadmap: Architect FPGA IP specifically for 4G/5G Radio Units, ensuring designs align with industry trends and long-term organizational strategy.
Strategic Design Choices: Set the standard for product excellence by selecting optimal components and design methodologies to meet aggressive cost and performance targets.
High-Complexity RTL Development: Lead the implementation of complex logic blocks using SystemVerilog, focusing on high-speed Ethernet and AXI protocol integration.
Model-Based Design: Utilize MATLAB and Simulink to model signal processing algorithms before translating them into hardware-efficient RTL.
Ensure Design Integrity: Oversee the full validation lifecycle, from UVM-based simulation to hands-on system-level testing and timing closure using Altera Quartus.
Hardware-Software Synergy: Partner closely with software and RF teams to ensure seamless interoperability between hardware logic and low-level software drivers.
Technical Authority: Act as the primary consultant on critical, high-impact projects, providing 'whiteboard-level' solutions to unusually complex engineering hurdles.
Team Mentorship: Provide technical guidance to junior engineers, fostering a culture of best practices in RTL coding and version control (Git).
Executive Communication: Bridge the gap between engineering and management by communicating project progress, risks, and technical visions to senior leadership.

Fulltime

Principal Quantum Systems Digital Design Engineer

Microsoft is the world’s center of expertise on topological quantum computing. W...

Location

United States , Redmond

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Electrical/Computer Engineering, or related field AND 3+ years experience in industry or in a research and development environment
OR Master's Degree in Physics, Electrical/Computer Engineering, or related field AND 4+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Electrical/Computer Engineering, or related field AND 6+ years experience in industry or in a research and development environment
OR equivalent experience
6+ years programming experience in related programming languages
6+ years experience in a collaborative environment
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
Ability to work in an "AI first" environment using modern AI tools to accelerate discovery through hardware development
Familiarity with designing and building AI agents/copilots that assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval

Job Responsibility

Design & implement RTL for streaming, low‑latency pipelines (e.g., readout classifiers, syndrome aggregation, and QEC decoder kernels) in Verilog/SystemVerilog, including resource/performance trade‑offs and power/thermal considerations
Design and implement high‑speed interconnects between subsystems (AXI4/AXI‑Stream, JESD204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring‑up, and throughput/latency tuning
Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi‑domain timing closure, async FIFOs, metastability analysis) for deterministic performance
Co‑design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams
contribute to system‑level design reviews
Verification and validation: develop simulation and constrained‑random tests (SV/UVM or equivalent), build on‑board diagnostics (ILA/ChipScope), and execute lab bring‑up with scopes, VNAs, LA/SC, and RF instruments
Tool flow & CI: own synthesis/implementation (Vivado/Vitis or Quartus/Prime), timing sign‑off, and reproducible, scripted builds (Tcl/Python) integrated with Git/Azure DevOps CI/CD
Quality & documentation: produce clear design docs, interface specs, and bring‑up guides
participate in rigorous code/design reviews and post‑silicon/post‑fabrication retros

Fulltime

New

Full-time Footwear Sales Assistant

Bring energy, passion and standout service as a Sales Assistant at JD Sports. Co...

Location

Australia , Chermside

Salary:

Not provided

JD Sports Australia & New Zealand

Expiration Date

Until further notice

Requirements

Customer service experience within retail, hospitality or like industry
Ability to provide excellent service and go above & beyond
Passionate about sports fashion or has a knowledge of key brands
A positive can-do attitude and ability to work as a team
Thrives in a fast paced, ever-changing environment
Enthusiastic to overcome challenges and learn new skills
Strong communication skills, someone who thrives through engagement with customers and team work
Ability to multi-task
Flexibility to work across various shifts, including weekends and holidays, based on store needs

Job Responsibility

Act as a brand ambassador, always showing positivity and professionalism
Gain and maintain up to date product knowledge to best assist our customers
Provide personalised 1:1 customer service
Assist customers with all queries and process sales
Work in collaboration with the wider Management and store team to achieve KPI's and targets
Support wider team with ad hoc tasks, including VM set up, store cleanliness and presentation etc
Escalate any customer complaints to management
Consistently complete any mandatory training relevant to product, policy & procedure etc

What we offer

Work in a dynamic business and engage with some of the best product and biggest sports fashion brands in the market
Training and development opportunities to kickstart, evolve and shape your career
Opportunity to progress across all areas of the business in a wide array of roles including Retail, Support Office, and our Distribution Centre
Access to our attractive staff discount
Access to our Employee Assistance Program & Mental Health champions
One month paid parental leave for full-time employees

Fulltime

New

Registered Service Manager

Location

United Kingdom , Falkirk

Salary:

35000.00 GBP / Year

360 Resourcing Solutions

Expiration Date

Until further notice

Requirements

A recognised Health & Social Care qualification (minimum Registered Manager's Award or equivalent management qualification)
Significant management experience within health, social care, or the independent sector
Experience managing people, budgets, and operational performance
Knowledge of legislation and standards affecting care service delivery
Strong leadership, communication, and organisational skills
A passion for delivering outstanding person-centred support
IT skills including email and Excel
The ability to work independently and motivate teams effectively

Job Responsibility

Provide dynamic leadership and support to operational staff across the Falkirk locality
Ensure delivery of high-quality, person-centred services within the Care Home
Oversee compliance with Care Inspectorate standards, Health & Safety requirements, and organisational policies
Manage staff supervision, probation reviews, team meetings, and mandatory training compliance
Monitor staffing, attendance, absence management, and workforce development
Ensure person-centred plans and risk assessments are regularly reviewed and maintained
Drive continuous improvement through Service Improvement Plans and Outcome Assessment Tools
Promote positive partnerships with families, professionals, and external agencies
Ensure effective use of systems including One Touch and EPIC recordings
Manage operational performance, budgets, and resources effectively

What we offer

A rewarding and meaningful career
Supportive leadership and development opportunities
The chance to positively impact people's lives every day
Opportunities for career progression
Work within a values-led organisation committed to person-centred care

Fulltime

New

AO4 Project Support Officer

Randstad is excited to partner with a key State Government Department to find an...

Location

Australia , Buderim

Salary:

60.00 - 65.00 AUD / Hour

Randstad

Expiration Date

June 07, 2026

Requirements

High-level competency in Microsoft 365, particularly Word, Excel, and PowerPoint
A basic understanding of procurement and finance
The ability to maintain effective relationships between internal and external stakeholders
A professional approach to work with a focus on transparency, accountability, and quality results
A mindset that embraces new ideas and makes considered, ethical decisions within a project context

Job Responsibility

Act as the primary interface for monitoring and tracking team responses, ensuring priority items are addressed promptly
Assist in developing procurement documents for contractor roles and projects, ensuring timely processing and adherence to policy
Capture key operational information, update registers, and assist with reporting to help the team prioritise backlogs effectively
Perform data entry within asset systems (ROAR) to ensure high-quality information is assigned to infrastructure assets

What we offer

Super
Career Growth: Unique opportunity to learn specialist skills and gain in-demand government experience
Room to grow and learn in the team

Principal FPGA / RTL Design Engineer

Silvus Technologies (International)

Location:
United States , Irvine

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
December 12, 2025

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