CrawlJobs Logo

Principal FPGA / RTL Design Engineer

silvustechnologies.com Logo

Silvus Technologies (International)

Location Icon

Location:
United States , Irvine

Category Icon

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

165000.00 - 250000.00 USD / Year

Job Description:

The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D. These are exciting projects aimed at addressing challenging real-world communication needs.

Job Responsibility:

  • Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks
  • RTL coding, simulation, and test bench development
  • FPGA synthesis and timing closure
  • Hardware verification and troubleshooting
  • familiarity with logic analyzers
  • Provide support to the RF and Software Engineering Teams

Requirements:

  • Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant fields
  • Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
  • 8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or relevant fields
  • Demonstrated experience with fixed point binary arithmetic and digital signal processing designs
  • Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
  • Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs
  • Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
  • Must be a U.S. Citizen due to clients under U.S. government contracts

Nice to have:

  • M.S. or Ph.D. degree in Electrical Engineering, Computer Science, or relevant fields
  • Basic MATLAB skills
  • Solid knowledge and understanding of scripting languages such as Perl and Python
  • Strong communication and presentation skills
  • Experience with wireless communication systems on FPGA or ASIC designs

Additional Information:

Job Posted:
December 12, 2025

Employment Type:
Fulltime
Work Type:
Hybrid work
Job Link Share:

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for Principal FPGA / RTL Design Engineer

Principal FPGA / RTL Design Engineer - Signal Processing

Participate in all aspects of the research and development process from concept ...
Location
Location
United States , Los Angeles
Salary
Salary:
165000.00 - 250000.00 USD / Year
silvustechnologies.com Logo
Silvus Technologies (International)
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
  • Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
  • 8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields
  • Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs
  • Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
  • Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs
  • Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
  • Must be U.S. Person (U.S. Citizen, or Permanent Resident) due to clients under U.S. federal contracts
  • All employment is contingent upon the successful clearance of a background check
Job Responsibility
Job Responsibility
  • Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks
  • RTL coding, simulation, and test bench development
  • FPGA synthesis and timing closure
  • Hardware verification and troubleshooting
  • familiarity with logic analyzers
  • Provide support to the RF and Software Engineering Teams
  • Fulltime
Read More
Arrow Right

Principal FPGA / RTL Design Engineer - Signal Processing

Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who ...
Location
Location
United States , Irvine
Salary
Salary:
165000.00 - 250000.00 USD / Year
silvustechnologies.com Logo
Silvus Technologies (International)
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields
  • Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
  • 8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields
  • Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs
  • Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
  • Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs
  • Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
  • Must be a U.S. Citizen due to clients under U.S. government contracts
  • All employment is contingent upon the successful clearance of a background check
Job Responsibility
Job Responsibility
  • Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks
  • RTL coding, simulation, and test bench development
  • FPGA synthesis and timing closure
  • Hardware verification and troubleshooting
  • familiarity with logic analyzers
  • Provide support to the RF and Software Engineering teams
  • Fulltime
Read More
Arrow Right

Senior FPGA Architect / Principal FPGA Engineer

Senior FPGA Architect / Principal FPGA Engineer – Real-Time Processing Systems
Location
Location
Canada , Ottawa
Salary
Salary:
Not provided
myticas.com Logo
Myticas Consulting
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Architect-level FPGA expertise designing high-performance real-time processing systems and complex programmable logic architectures
  • Advanced RTL development using Verilog / SystemVerilog for high-throughput pipelines, accelerators, and timing-sensitive hardware logic
  • Experience building FPGA-based SoC architectures including AXI/Avalon fabrics, DMA engines, memory controllers, and multi-clock domain designs
  • Strong background in high-bandwidth data-path design, resource utilization optimization, timing feasibility, and device architecture trade-offs
  • Hands-on expertise with Xilinx UltraScale+/MPSoC and/or Intel FPGA families (Arria, Stratix, Agilex) and associated development toolchains
  • Deep experience integrating high-speed interfaces such as PCIe, Ethernet, and high-speed serial transceivers (SERDES)
  • Familiarity with video/media transport or other latency-sensitive real-time processing environments involving high data throughput
  • Proven ability to drive timing closure, synthesis, floorplanning, constraint management, and place-and-route optimization
  • Strong verification leadership including simulation-driven validation, UVM environments, constrained-random testing, and coverage-driven methodologies
  • Practical lab experience performing FPGA bring-up, system integration, and hardware debug using scopes, logic analyzers, and embedded debug tools
  • Fulltime
Read More
Arrow Right
New

Principal FPGA Design Engineer - 4G/5G Radio Systems

Are you a FPGA Design Engineer looking for a new opportunity? Are you looking fo...
Location
Location
Canada , Kanata
Salary
Salary:
62.19 - 72.43 USD / Hour
https://www.randstad.com Logo
Randstad
Expiration Date
June 29, 2026
Flip Icon
Requirements
Requirements
  • 7+ Years of RTL Expertise: Proven track record in high-complexity FPGA design, specifically using SystemVerilog or Verilog. (Note: Candidate must be willing to work exclusively in a non-VHDL environment).
  • Altera/Intel Toolchain: Mastery of Quartus Prime for synthesis, place-and-route, and timing closure on high-density FPGAs.
  • DSP Modeling: Proficiency in MATLAB and Simulink for algorithmic modeling and fixed-point simulation prior to RTL implementation.
  • Protocol Mastery: Deep expertise in AXI (AXI4-Stream, AXI4-Lite) and Ethernet (10G/25G/100G) protocol implementation.
  • High Speed Interfaces: Practical experience with JESD204B/C, PCIe, and multi-gigabit SERDES transceivers.
  • Synchronization: Understanding of timing and synchronization protocols, such as PTP (IEEE 1588) and SyncE.
  • Wireless Infrastructure: Direct experience developing Radio Units (RU) or Massive MIMO systems.
  • Industry Standards: Functional knowledge of 3GPP physical layer specifications and O-RAN (Open RAN) Fronthaul interfaces (eCPRI/CPRI).
  • Signal Processing: Experience implementing Digital Up/Down Conversion (DUC/DDC), Crest Factor Reduction (CFR), or Digital Pre-Distortion (DPD) in hardware.
  • Advanced Verification: Experience with UVM (Universal Verification Methodology) and constrained-random testing to ensure 'first-time-right' silicon/FPGA bitstreams.
Job Responsibility
Job Responsibility
  • Define System Requirements: Translate high-level customer needs and 3GPP/O-RAN standards into detailed functional specifications for the entire FPGA ecosystem.
  • Drive 5G Roadmap: Architect FPGA IP specifically for 4G/5G Radio Units, ensuring designs align with industry trends and long-term organizational strategy.
  • Strategic Design Choices: Set the standard for product excellence by selecting optimal components and design methodologies to meet aggressive cost and performance targets.
  • High-Complexity RTL Development: Lead the implementation of complex logic blocks using SystemVerilog, focusing on high-speed Ethernet and AXI protocol integration.
  • Model-Based Design: Utilize MATLAB and Simulink to model signal processing algorithms before translating them into hardware-efficient RTL.
  • Ensure Design Integrity: Oversee the full validation lifecycle, from UVM-based simulation to hands-on system-level testing and timing closure using Altera Quartus.
  • Hardware-Software Synergy: Partner closely with software and RF teams to ensure seamless interoperability between hardware logic and low-level software drivers.
  • Technical Authority: Act as the primary consultant on critical, high-impact projects, providing 'whiteboard-level' solutions to unusually complex engineering hurdles.
  • Team Mentorship: Provide technical guidance to junior engineers, fostering a culture of best practices in RTL coding and version control (Git).
  • Executive Communication: Bridge the gap between engineering and management by communicating project progress, risks, and technical visions to senior leadership.
  • Fulltime
Read More
Arrow Right

Principal Quantum Systems Digital Design Engineer

Microsoft is the world’s center of expertise on topological quantum computing. W...
Location
Location
United States , Redmond
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Physics, Electrical/Computer Engineering, or related field AND 3+ years experience in industry or in a research and development environment
  • OR Master's Degree in Physics, Electrical/Computer Engineering, or related field AND 4+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Physics, Electrical/Computer Engineering, or related field AND 6+ years experience in industry or in a research and development environment
  • OR equivalent experience
  • 6+ years programming experience in related programming languages
  • 6+ years experience in a collaborative environment
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
  • Ability to work in an "AI first" environment using modern AI tools to accelerate discovery through hardware development
  • Familiarity with designing and building AI agents/copilots that assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval
Job Responsibility
Job Responsibility
  • Design & implement RTL for streaming, low‑latency pipelines (e.g., readout classifiers, syndrome aggregation, and QEC decoder kernels) in Verilog/SystemVerilog, including resource/performance trade‑offs and power/thermal considerations
  • Design and implement high‑speed interconnects between subsystems (AXI4/AXI‑Stream, JESD204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring‑up, and throughput/latency tuning
  • Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi‑domain timing closure, async FIFOs, metastability analysis) for deterministic performance
  • Co‑design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams
  • contribute to system‑level design reviews
  • Verification and validation: develop simulation and constrained‑random tests (SV/UVM or equivalent), build on‑board diagnostics (ILA/ChipScope), and execute lab bring‑up with scopes, VNAs, LA/SC, and RF instruments
  • Tool flow & CI: own synthesis/implementation (Vivado/Vitis or Quartus/Prime), timing sign‑off, and reproducible, scripted builds (Tcl/Python) integrated with Git/Azure DevOps CI/CD
  • Quality & documentation: produce clear design docs, interface specs, and bring‑up guides
  • participate in rigorous code/design reviews and post‑silicon/post‑fabrication retros
  • Fulltime
Read More
Arrow Right
New

Osd Clerk

The OS&D clerk is in charged of documenting any Overages (quantities received ar...
Location
Location
Canada , Saint-Laurent
Salary
Salary:
22.00 - 24.00 CAD / Hour
https://www.randstad.com Logo
Randstad
Expiration Date
July 02, 2026
Flip Icon
Requirements
Requirements
  • Good attention to detail and ability to multitask
  • Great organizational skills
  • 1 year experience in a transport, warehouse or logistics industry (asset)
  • Safety boots required
  • English with a functional French or French with a functional English
Job Responsibility
Job Responsibility
  • Data entry of overages, shortages and damages of shipping items received
  • Review of documents regarding orders and ensuring accuracy, documenting any problems
  • Verifying all orders at the dock
  • Produce and report different types of documents and reports
  • Administrative support when required
What we offer
What we offer
  • Located in St Laurent
  • Contract 6 months with possibility of permanency afterwards
  • Weekly pay
  • Parking on site
  • Monday to Friday 7am to 3:30pm
  • Start date ASAP
  • Salary between 22-24$/hr
  • Unionized
  • 22.82$/hr + 50 cent increase every 6 months
  • Insurance package 100% covered by employer
  • Fulltime
Read More
Arrow Right
New

Footwear Supervisor

Lead from the front as a JD Sports Supervisor! Drive sales, coach your team, and...
Location
Location
Australia , Chermside
Salary
Salary:
Not provided
jd-sports.com.au Logo
JD Sports Australia & New Zealand
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Minimum 2 years of experience within retail or like industry
  • Passionate about delivering an amazing service experience for our customers
  • Positive attitude, with capacity to create a motivating environment for your team
  • Excellent time management skills to ensure daily priorities are executed in a timely manner
  • Strong interpersonal and communication skills, someone who thrives in social situations through engagement with customers and team members
Job Responsibility
Job Responsibility
  • Model exceptional customer service, every customer, every time
  • Coach team to deliver exceptional service and a 'service over task' environment
  • Drive conversion, sales and KPI performance
  • Work with BOH team to deliver shop floor product availability
  • Uphold company retail standards and deliver store visual excellence
  • Support management team to improve financial performance within your department
  • Support management team to deliver all internal and external profit protection processes
  • Support with new team member role inductions and on-going team training
What we offer
What we offer
  • Access to attractive staff discount (also for friends and family)
  • Training and development opportunities to kickstart, evolve and shape your career
  • Opportunity to progress across all areas of the business in a wide array of roles including Retail, Support Office, and our Distribution Centre
  • Access to Employee Assistance Program & Mental Health champions
  • One month paid parental leave for full-time employees
  • Fulltime
Read More
Arrow Right
New

Teaching Assistant

Join Our Passionate Team and Make a Real Difference! Are you looking for a schoo...
Location
Location
United Kingdom , Shoreham-by-Sea
Salary
Salary:
Not provided
https://www.randstad.com Logo
Randstad
Expiration Date
June 13, 2026
Flip Icon
Requirements
Requirements
  • The ability to work with learners that have various learning difficulties
  • A willingness to learn and build relationships with learners
  • The ability to work as an individual and as a part of the team
  • Flexibility in their approach to education
  • Own means of transport
  • GSCE Maths and English
Job Responsibility
Job Responsibility
  • Providing teaching assistance to the teacher defined according to weekly/daily/seasonal planning of the teacher
  • Working 1:1 with students
  • Providing group and/or individual activities, planned by the teacher
  • Working individually with learners/students to develop work
  • Supporting the general well being of learners within the structure of the school
  • Monitoring and evaluate students learning under the guidance of the teacher
  • Assisting teachers in the use of relevant management strategies to ensure a purposeful environment for teaching and learning to take place
  • Supporting all learners in their planned structured work in all curriculum areas
What we offer
What we offer
  • Fully funded training and qualifications
  • On site parking
  • Extensive grounds
  • Free hot lunch from the onsite cafeteria
  • Team days and events
  • Supportive management
  • Brilliant career progression opportunities
  • A unique teaching approach
  • Fulltime
Read More
Arrow Right