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Are you a FPGA Design Engineer looking for a new opportunity? Are you looking for a new contract in the Ottawa area? We are pleased to offer you a new contract opportunity for you to consider working with an enterprise client! - Start: ASAP - Estimated length: 6 months - Location: Ottawa - Hybrid role (must be able to work out of the Kanata office, approx. 3 days per week)
Job Responsibility:
Define System Requirements: Translate high-level customer needs and 3GPP/O-RAN standards into detailed functional specifications for the entire FPGA ecosystem.
Drive 5G Roadmap: Architect FPGA IP specifically for 4G/5G Radio Units, ensuring designs align with industry trends and long-term organizational strategy.
Strategic Design Choices: Set the standard for product excellence by selecting optimal components and design methodologies to meet aggressive cost and performance targets.
High-Complexity RTL Development: Lead the implementation of complex logic blocks using SystemVerilog, focusing on high-speed Ethernet and AXI protocol integration.
Model-Based Design: Utilize MATLAB and Simulink to model signal processing algorithms before translating them into hardware-efficient RTL.
Ensure Design Integrity: Oversee the full validation lifecycle, from UVM-based simulation to hands-on system-level testing and timing closure using Altera Quartus.
Hardware-Software Synergy: Partner closely with software and RF teams to ensure seamless interoperability between hardware logic and low-level software drivers.
Technical Authority: Act as the primary consultant on critical, high-impact projects, providing 'whiteboard-level' solutions to unusually complex engineering hurdles.
Team Mentorship: Provide technical guidance to junior engineers, fostering a culture of best practices in RTL coding and version control (Git).
Executive Communication: Bridge the gap between engineering and management by communicating project progress, risks, and technical visions to senior leadership.
Competitive Intelligence: Conduct technical evaluations and competitive analyses to ensure the product remains a leader in the wireless infrastructure market.
Requirements:
7+ Years of RTL Expertise: Proven track record in high-complexity FPGA design, specifically using SystemVerilog or Verilog. (Note: Candidate must be willing to work exclusively in a non-VHDL environment).
Altera/Intel Toolchain: Mastery of Quartus Prime for synthesis, place-and-route, and timing closure on high-density FPGAs.
DSP Modeling: Proficiency in MATLAB and Simulink for algorithmic modeling and fixed-point simulation prior to RTL implementation.
Protocol Mastery: Deep expertise in AXI (AXI4-Stream, AXI4-Lite) and Ethernet (10G/25G/100G) protocol implementation.
High Speed Interfaces: Practical experience with JESD204B/C, PCIe, and multi-gigabit SERDES transceivers.
Synchronization: Understanding of timing and synchronization protocols, such as PTP (IEEE 1588) and SyncE.
Wireless Infrastructure: Direct experience developing Radio Units (RU) or Massive MIMO systems.
Industry Standards: Functional knowledge of 3GPP physical layer specifications and O-RAN (Open RAN) Fronthaul interfaces (eCPRI/CPRI).
Signal Processing: Experience implementing Digital Up/Down Conversion (DUC/DDC), Crest Factor Reduction (CFR), or Digital Pre-Distortion (DPD) in hardware.
Advanced Verification: Experience with UVM (Universal Verification Methodology) and constrained-random testing to ensure 'first-time-right' silicon/FPGA bitstreams.
Modern Version Control: High proficiency in Git/GitHub workflows for collaborative RTL development and continuous integration.
Architectural Vision: Ability to take a system-level concept and decompose it into high-performance FPGA subsystems.
Technical Leadership: Demonstrated experience mentoring junior designers and leading technical 'whiteboard' architectural reviews.
Strategic Thinking: Capability to analyze competitive landscape and industry trends to influence component selection and product cost-reduction strategies.