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Principal Engineer, RTL Design

India, Bangalore · Job Posted February 17, 2026
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Job Description

Enphase is looking for an experienced SoC and IP Subsystems design engineer to work on our next generation CPU subsystem or peripheral IP development and integration. The MCU will use the ARM CM4 core, so experience with that core is a must. We will also be integrating safety and security features into this next generation of MCU so a deep understanding of these SoC challenges is required. This position is in our ASIC Engineering Team - Bangalore, reporting to the Senior Director of ASIC engineering.

Job Responsibility

  • Architect, design and integrate our CPU Subsystem or peripheral Ips into our next generation of MCUs, including the safety and security features that are required by our applications
  • Responsible for defining the verification plans for these subsystems

Requirements

  • Deep understanding and experience in SoC micro architecture, IP Development, RTL and integration
  • Specific experience integrating the ARM CM4 and all the surrounding IP, like: AHB, AXI, RAM and ROM controllers, DMA controllers
  • Experience with the ARM Protection units is preferred
  • Experience with one of the “TrustZone” like IP from other vendors will be an added advantage
  • Experience with integrating high speed and high accuracy analog systems is a must
  • RTL Integration of SoC/Subsystems from IPs, ability to debug the issues in logic verification, act as liaison between Design and Place and Route teams is mandatory
  • Knowledge of all the Soft IP collateral and deliverables eg: Lint, CDC, UPF, timing constraints
  • Experience and ability to shape and direct our future IP and SoC integration methodology

Nice to have

Experience with one of the “TrustZone” like IP from other vendors will be an added advantage

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