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Principal Engineer Physical Design

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Microsoft Corporation

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Location:
Malaysia , Gelugor

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Category:
IT - Software Development

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Contract Type:
Not provided

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Salary:

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Job Description:

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Microsoft’s Compute Silicon & Manufacturing Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Physical Design Engineer to join the team.

Job Responsibility:

  • Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of complex partitions/subsytems through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification
  • Own complete PD execution of Sub-systems/Sub-chips instantiating/integrating multiple other physical partitions
  • Implement robust clock distribution solutions using appropriate methods that meet design requirements
  • Have close collaboration with RTL team (RTL2PD liaison) to help drive and resolve design issues related to block closure
  • Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach
  • Make independent and good technical trade-off decisions between power, area, and timing (PPA)
  • Lead, guide and coordinate with all sub-partitions PD owners to be able to take Subsystem/Subchip through PD (construction through signoff) closure
  • Collaborating and influencing various aspects of PD Methodology will also be key requirement in this role
  • Additionally drive key pieces of PD implementation methodology or specific areas such as Clocking/Low power optimization/Power & Performance methodology
  • Partner closely with PD flow/CAD team and PD methodology team
  • Be fully hands-on in your individual ownerships as individual contributor and collaborate cross-team on all aspects of SC/SS execution, integration & delivery
  • Be in individual contribution capacity with the requirement to lead, guide and mentor junior engineers on technical issues

Requirements:

  • BS/BE/BTech/MS/ME/MTech in Electronics or Microelectronics/VLSI, or Electrical Engineering
  • Min 15+ years of experience in semiconductor design
  • Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams
  • Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, EMIR closure and physical verification
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
  • This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Nice to have:

  • Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes
  • Technical led PD teams to deliver multiple PD partitions integrated in a subchip/subsystem, having excellent project management skills and ability to juggle multiple projects at once
  • Strong understanding of constraints generation, STA, timing optimization, and timing closure
  • In-depth understanding of design tradeoffs for power, performance, and area
  • Experience in driving PD implementation methodology and/or specific areas such as Clocking/Low power optimization/Power & Performance methodology will be key
  • Hands on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs
  • As an individual contributor demonstrating technically leadership and guide a team of multiple PD engineers to deliver a Sub-Chip/SoC is a mandatory requirement
  • Overall know how of PD-TFM, exposure and some hands-on experience with PD flows bring up/setup/flow flush and PD methodology will be a bonus
  • Experience in EDA tools such as Primetime, StarRC, Design Compiler, Fusion Compiler/ICC2, Innovus etc
  • Experience and knowledge of formal equivalency checks, LEC, LP, UPF, reliability, SI, and Noise
  • Strong problem-solving and data analysis skills
  • Automation skills using scripting languages such as Perl, TCL, or Python

Additional Information:

Job Posted:
February 18, 2026

Employment Type:
Fulltime
Work Type:
On-site work
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