Principal Engineer, ASIC Development Engineering (RTL Design) Job at Sandisk (Bengaluru)

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly skilled and experienced Principal Engineer to join our A...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field
8+ years of experience in ASIC development, with a proven track record of leading complex project
Hands on in IP / blocks / subsystem complex design in verilog / sysverilog
Strong digital design development and execution skills , solving bugs
Experience in grooming team of 1-4 engineers, interacting with many team
Deep expirience in debug , solving problem, see the architecture view, proposing solutions.
Hands-on experience with industry-standard EDA tools and design flows
Deep knowledge on PCIe, axi , DMA, AHB interfaces
Expertise in high-performance and low-power design techniques
Excellent communication skills, both verbal and written, with the ability to articulate complex technical concepts clearly

Job Responsibility

Design and implements IPs and subsystems
Dealing the best of class IPs for all SanDisk products

Fulltime

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
9+ years of experience in digital design, with a focus on RTL design for complex SoCs
Deep expertise in Verilog/SystemVerilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Experience with synthesis, static timing analysis, and DFT concepts
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Proven track record of leading technical teams and delivering successful silicon
Excellent analytical, problem-solving, and communication skills
Passion for innovation and delivering high-quality, scalable solutions

Job Responsibility

Define and review SoC architecture and design specifications
Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
Contribute to IP selection, evaluation, and integration in SoC designs
Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels

Fulltime

Principal Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This role will require access to information that is controlled for export under export control regulations
10+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure
8+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs
5+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug
5+ experience in Designing Fabric/Network On Chip or Networking ASICs or Complex Control Logic

Job Responsibility

Part of the design team driving many facets of high performance, high bandwidth designs
Working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis, and System on Chip (SOC) integration on different subsystems
Interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec

Fulltime

Principal Logic Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Establish yourself as an integral member of a digital logic design team for the development of AI components with focus on micro-architectural based functions and features
Be responsible for the logic design/Register Transfer Level (RTL) entry, design quality including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc., and timing closure of high-performance digital IP
Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent
Interface with physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design
Provide technical leadership through mentorship and strong teamwork

Fulltime

New

ASIC Principal Design Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...

Location

India , Bangalore

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Strong Verilog RTL coding skills
Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
Knowledge of high performance memory subsystems
Knowledge of multi-domain clock synchronization and high-speed serial interfaces
Strong problem solving and ASIC debugging skills
Excellent written and verbal communications skills
MSEE or BSEE is required with 8 plus years of experience

Job Responsibility

Define and architect high-performance blocks for the latest, most advanced networking ASICs
Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
Collaborate with the verification team in the development of the testplan and assist in debugging test failures
Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

ASIC Digital Design Principal Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

India , Bengaluru

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) or related field
Minimum 6 years of experience in bare metal firmware development and silicon testing
Strong understanding of digital design (RTL) and mixed-signal integration principles
Experience with structured firmware development, verification, and documentation processes
Proficiency in project execution, from initial specification through to final testing and validation
Knowledge of SerDes standards and scripting (Shell/Python) is a strong advantage

Job Responsibility

Designing, developing, and testing bare metal firmware for advanced mixed-signal ASICs, with a focus on high-speed SerDes products
Collaborating with analog and digital teams to define specifications and integration requirements for IP blocks and system-on-chip (SoC) solutions
Executing structured firmware development processes, including verification and thorough documentation of design flows
Performing functional and performance tests on prototype test-chips to ensure robust operation and compliance with design specifications
Supporting customer teams by providing technical expertise, troubleshooting, and guidance throughout the product lifecycle
Contributing to project planning, tracking milestones, and ensuring timely delivery of high-quality deliverables
Engaging in continuous learning to stay abreast of industry advancements in SerDes standards, scripting, and digital design methodologies

What we offer

Comprehensive medical and healthcare plans that work for you and your family
Time Away in addition to company holidays, we have ETO and FTO Programs
Family Support maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement Plans save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

New

Principal Engineer, ASIC Development Engineering (PD Methodology & CAD Flow)

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...

Location

India , Hyderabad

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

8+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs
Deep, hands-on understanding of complete PD flow, including: Synthesis, Logical Equivalence Checking (LEC), DFT insertion and integration, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis
Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA
Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes
M.Tech in VLSI Design or a related field (or equivalent industry experience)
Proficiency in scripting and automation using TCL, Perl, and/or Python
Experience working in multi-project, high-complexity environments with tight schedules

Job Responsibility

Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices
Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions
Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence
Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules
Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability
Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity
Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges

Fulltime

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
Ability to meet Microsoft, customer and/or government security screening requirements
Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Ability to provide proof of country of citizenship or proof of US residency or other protected status for export control assessment
Bachelor's or master’s in electrical or computer engineering or related field with 10+ years of experience
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeout of complex ASICs in leading edge process node technology
8+ years of hands-on experience in EDA vendor tools such as Fusion Compiler, VCLP, Primetime, Formality, or Cadence Innovus and Conformal

Job Responsibility

Lead a team in defining implementation and execution plan for a schip/SOC
Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
Drive the team to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
Optimizing technology, libraries, physical design, RTL design, and architecture
Collaborate with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects
Provide technical guidance and mentorship to team members
Oversee the development and implementation of physical design flows and methodologies
Collaborate with cross-functional teams to address design challenges and optimize for manufacturability
Monitor progress, identify risks, and implement mitigation strategies
Keep abreast of the latest industry trends, tools, and techniques in physical design

Fulltime

Principal Engineer, ASIC Development Engineering (RTL Design)

Sandisk

Location:
India , Bengaluru

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
January 11, 2026

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