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Principal Engineer will contribute to the design and development of IO and high‑speed interface solutions for next‑generation SoCs in advanced CMOS technology nodes.
Job Responsibility:
Contribute to the design and development of IO and high‑speed interface solutions for next‑generation SoCs in advanced CMOS technology nodes
Participate in the design, and implementation of IO and high‑speed interface solutions for SanDisk ASIC controllers
Evaluate design approaches, implement blocks at the circuit and RTL levels as applicable, perform detailed analysis, and drive design closure with focus on quality and schedule
Collaborate with layout engineers by providing clear guidance, performing schematic‑layout reviews, and ensuring design robustness and layout quality
Support SOC integration activities, debug integration issues, and participate in post‑tapeout efforts including silicon characterization and performance validation
Provide technical guidance to junior engineers, support their ramp‑up, and contribute to fostering a culture of technical excellence
Contribute ideas for design improvements, propose enhancements to design methodologies, and support the development of efficient flows and best practices
Requirements:
Bachelor’s or Master’s degree in Electronics & Telecommunication or Electrical Engineering
9+ years of hands-on experience in High‑Speed I/O design
Strong hands-on experience in TX/RX design for high-speed memory interfaces such as DDR4, DDR5, and HBM, including comprehensive timing budget analysis
Practical experience with IO standards and IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration circuits, HV‑tolerant and fail‑safe IOs, and crystal oscillators
Expertise in ESD circuit design, including familiarity with ESD guidelines, methodologies, and best practices across multiple process nodes
Proficient with industry‑standard custom design tools such as Cadence Virtuoso, Synopsys Custom Compiler, and SPICE simulators (HSPICE, Spectre, FineSim), including statistical simulation methodologies
Deep understanding of CMOS technologies, including FinFET nodes and awareness of associated DSM (Deep Sub‑Micron) challenges
Highly analytical mindset with the ability to work effectively in multidisciplinary teams
Creative, innovative thinker with strong personal ownership and attention to detail
Strong theoretical foundation complemented by a pragmatic, solution‑oriented approach
Excellent verbal and written communication skills with experience collaborating across global teams
Strong documentation and presentation skills
Nice to have:
Exposure to creating EDA models such as Verilog models, Liberty (.lib) files, etc., is beneficial