Principal Engineer - ASIC development Engineering (DFT) Job at Sandisk (Bengaluru)

Principal Engineer, ASIC Development Engineering (PD Methodology & CAD Flow)

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...

Location

India , Hyderabad

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

8+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs
Deep, hands-on understanding of complete PD flow, including: Synthesis, Logical Equivalence Checking (LEC), DFT insertion and integration, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis
Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA
Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes
M.Tech in VLSI Design or a related field (or equivalent industry experience)
Proficiency in scripting and automation using TCL, Perl, and/or Python
Experience working in multi-project, high-complexity environments with tight schedules

Job Responsibility

Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices
Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions
Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence
Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules
Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability
Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity
Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges

Fulltime

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
9+ years of experience in digital design, with a focus on RTL design for complex SoCs
Deep expertise in Verilog/SystemVerilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Experience with synthesis, static timing analysis, and DFT concepts
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Proven track record of leading technical teams and delivering successful silicon
Excellent analytical, problem-solving, and communication skills
Passion for innovation and delivering high-quality, scalable solutions

Job Responsibility

Define and review SoC architecture and design specifications
Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
Contribute to IP selection, evaluation, and integration in SoC designs
Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels

Fulltime

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
9+ years of experience in digital design, with a focus on RTL design for complex SoCs
Deep expertise in Verilog/SystemVerilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Experience with synthesis, static timing analysis, and DFT concepts
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Proven track record of leading technical teams and delivering successful silicon
Excellent analytical, problem-solving, and communication skills
Passion for innovation and delivering high-quality, scalable solutions

Job Responsibility

Define and review SoC architecture and design specifications
Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
Contribute to IP selection, evaluation, and integration in SoC designs
Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels

Fulltime

Principal Logic Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Establish yourself as an integral member of a digital logic design team for the development of AI components with focus on micro-architectural based functions and features
Be responsible for the logic design/Register Transfer Level (RTL) entry, design quality including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc., and timing closure of high-performance digital IP
Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent
Interface with physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design
Provide technical leadership through mentorship and strong teamwork

Fulltime

Principal Quantum Analog Design Lead

As a Principal Quantum Analog Design Lead in the Quantum 1st Party Hardware Appl...

Location

United States , Redmond

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment
OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations
Ability to leverage AI tools to drive innovation and efficiency
Ability to work in an AI-first environment using modern AI tools to accelerate discovery through hardware development

Job Responsibility

Coordinate interactions with Quantum Qubit design and Measurement teams to define specifications, architecture, and micro-architecture for Analog IP blocks
Own and drive the development of analog IP, including microarchitecture, schematic entry, and verification of complex blocks to meet stringent power, performance, and timing goals
Create test plans for verification and post-silicon validation and characterization
Design and validate analog blocks in simulation, both pre- and post-layout
Drive design reviews, status reports, and schedules to deliver against internal end-to-end milestone quality
Coordinate the work of other Analog Designers and Verification teams, audit their output, and provide guidance and direction to deliver high-quality results
Develop basic test benches and support verification, Design For Test (DFT), and post-silicon validation activities
Collaborate effectively with architects, analog mixed-signal designers, verification engineers, and physical design, DFT, and other front-end design teams
Align development methodologies with wider teams and drive continuous improvement to Analog Design Flow and development processes for at-scale execution

Fulltime

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

India , Bangalore

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Bachelor's or master’s in electrical or computer engineering or related field with 15+ years of experience
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeouts of complex ASICs in leading edge technology
Ability to meet Microsoft, customer and/or government security screening requirements
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Lead a team in defining implementation and execution plan for a schip/SOC
Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
Drive the to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
Optimizing technology, libraries, physical design, RTL design, and architecture
Leading the team in defining the implementation and execution plan for a subchip/SOC
Collaborating with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects to ensure a cohesive plan
Executing the defined plan to ensure successful tapeout of the subchip/SOC
Driving the team to achieve the best performance, power, and area (PPA) for AI system-on-chips
Optimizing technology choices, libraries, physical design methodologies, RTL design strategies, and architectural decisions to meet performance targets
Ensuring that the physical design aspects align with the overall project goals and timelines

Fulltime

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
Ability to meet Microsoft, customer and/or government security screening requirements
Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Ability to provide proof of country of citizenship or proof of US residency or other protected status for export control assessment
Bachelor's or master’s in electrical or computer engineering or related field with 10+ years of experience
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeout of complex ASICs in leading edge process node technology
8+ years of hands-on experience in EDA vendor tools such as Fusion Compiler, VCLP, Primetime, Formality, or Cadence Innovus and Conformal

Job Responsibility

Lead a team in defining implementation and execution plan for a schip/SOC
Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
Drive the team to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
Optimizing technology, libraries, physical design, RTL design, and architecture
Collaborate with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects
Provide technical guidance and mentorship to team members
Oversee the development and implementation of physical design flows and methodologies
Collaborate with cross-functional teams to address design challenges and optimize for manufacturability
Monitor progress, identify risks, and implement mitigation strategies
Keep abreast of the latest industry trends, tools, and techniques in physical design

Fulltime

New

Social Worker – Fostering - Family and Friends Team

Are you passionate about working with Family and Friends Carers and improving th...

Location

United Kingdom , Aylesbury

Salary:

40109.00 - 47629.00 GBP / Year

Buckinghamshire Council

Expiration Date

July 20, 2026

Requirements

Social work qualification
Active SWE registration
Completed ASYE
Working knowledge of legislation and guidance which applies to family and friends work
Experience of working in looked after children or with foster carers
Knowledge of research, inquiries and recent studies affecting this sector of service and an ability to monitor its application in practice
Strong written communication skills
Minimum of 2 years post qualifying experience
Experience and competence in working with the courts and providing written and verbal evidence

Job Responsibility

Deliver targeted and specialist social work services in the area of Kinship Care
Clarify eligibility and undertake statutory social work assessments
Promote the safety and well-being of children and young people
Assess and support prospective Family and Friends carers in line with Fostering Regulations and court proceedings
Hold a manageable caseload of SG and Reg24 assessments
Provide carer support
Work within statutory guidelines and fostering regulations
Assist with duty with opportunities to deliver training, run support groups and be involved in the organisation of carer events
Support the development and growth of the service

What we offer

Market premium of £2,750 per annum for Grade 7
Golden Hello payment after one years service (£1,000 for Grade 6, £2,125 for Grade 7)
Competitive salary with a market increment
Annual leave up to 30 days per year
Opportunity to buy further leave
Up to 15 days per year training, learning and development offer
Free parking across all office sites
Relocation packages available
Generous employer pension contribution
Discounts on Cafés, restaurants and shops

Fulltime

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Principal Engineer - ASIC development Engineering (DFT)

Job Description

Job Responsibility

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