CrawlJobs Logo

Principal Engineer - ASIC development Engineering (DFT)

sandisk.com Logo

Sandisk

Location Icon

Location:
India , Bengaluru

Category Icon
Category:
IT - Software Development

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

Not provided
Save Job
Save Icon
Apply Position

Job Description:

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic team of engineers to develop the next-generation Flash Controllers. As an SoC DFT Engineer, you will be responsible for defining and implementing industry leading DFT solutions, with emphasis on SCAN, MBIST, BSDL etc. The ideal candidate will have a deep understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG & Simulation expertise.

Job Responsibility:

  • Understanding of DFT Architecture and SoC development flows
  • Leading different DFT tasks and providing solutions for DFT problems
  • Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs
  • Working closely with the internal DFT team and ensure timelines and quality of deliveries are met
  • Work closely with the Product Engineering team and understand the test requirements, get involved in silicon debugs
  • Continuously monitor the enhancement needs on internal DFT and ensure all flow requirements are implemented by CAD
  • Provide training and mentorship to the team as needed

Requirements:

  • B.Tech / M.Tech / Phd in Electronics, Computer science or Electrical Engineering
  • Minimum 9 years of experience in DFT
  • Strong understanding of DFT Architecture
  • Experience in SoC DFT architecture, DFT IP development and DFT methodology
  • Proven track record of driving DFT architecture convergence in semiconductor designs
  • Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs)
  • Proficiency in SCAN, MBIST implementation
  • Solid understanding of JTAG & BSDL standards
  • Good understanding on Test clocking requirements, Test mode timing closure
  • Proficiency in silicon debugs, Shmoo analysis, and understand Test engineering requirements
  • Capable of setting up MBIST, ATPG and Simulation environments and debug issues independently
  • Good understanding of test constraints and support the STA teams for test mode timing closure
  • Capable of translating test requirements into Test IPs and pioneer any new test hardware implementations
  • Good analytical and problem-solving skills
  • Strong communication skills and the ability to work effectively in cross-functional teams

Additional Information:

Job Posted:
January 11, 2026

Employment Type:
Fulltime
Work Type:
On-site work
Icon
Sandisk - All Job Offers
Job Link Share:
Copy Link Icon
Facebook Icon Twitter Icon LinkedIn Icon

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for Principal Engineer - ASIC development Engineering (DFT)

Principal Engineer, ASIC Development Engineering (PD Methodology & CAD Flow)

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...
Location
Location
India , Hyderabad
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 8+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs
  • Deep, hands-on understanding of complete PD flow, including: Synthesis, Logical Equivalence Checking (LEC), DFT insertion and integration, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis
  • Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA
  • Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes
  • M.Tech in VLSI Design or a related field (or equivalent industry experience)
  • Proficiency in scripting and automation using TCL, Perl, and/or Python
  • Experience working in multi-project, high-complexity environments with tight schedules
Job Responsibility
Job Responsibility
  • Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices
  • Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions
  • Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence
  • Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules
  • Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability
  • Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity
  • Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges
  • Fulltime
Read More
Arrow Right

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
  • 9+ years of experience in digital design, with a focus on RTL design for complex SoCs
  • Deep expertise in Verilog/SystemVerilog
  • Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
  • Experience with synthesis, static timing analysis, and DFT concepts
  • Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
  • Proven track record of leading technical teams and delivering successful silicon
  • Excellent analytical, problem-solving, and communication skills
  • Passion for innovation and delivering high-quality, scalable solutions
Job Responsibility
Job Responsibility
  • Define and review SoC architecture and design specifications
  • Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
  • Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
  • Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
  • Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
  • Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
  • Contribute to IP selection, evaluation, and integration in SoC designs
  • Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels
  • Fulltime
Read More
Arrow Right

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
  • 9+ years of experience in digital design, with a focus on RTL design for complex SoCs
  • Deep expertise in Verilog/SystemVerilog
  • Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
  • Experience with synthesis, static timing analysis, and DFT concepts
  • Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
  • Proven track record of leading technical teams and delivering successful silicon
  • Excellent analytical, problem-solving, and communication skills
  • Passion for innovation and delivering high-quality, scalable solutions
Job Responsibility
Job Responsibility
  • Define and review SoC architecture and design specifications
  • Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
  • Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
  • Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
  • Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
  • Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
  • Contribute to IP selection, evaluation, and integration in SoC designs
  • Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels
  • Fulltime
Read More
Arrow Right

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Raleigh
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • Ability to provide proof of country of citizenship or proof of US residency or other protected status for export control assessment
  • Bachelor's or master’s in electrical or computer engineering or related field with 10+ years of experience
  • Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
  • Experience in tapeout of complex ASICs in leading edge process node technology
  • 8+ years of hands-on experience in EDA vendor tools such as Fusion Compiler, VCLP, Primetime, Formality, or Cadence Innovus and Conformal
Job Responsibility
Job Responsibility
  • Lead a team in defining implementation and execution plan for a schip/SOC
  • Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
  • Drive the team to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
  • Optimizing technology, libraries, physical design, RTL design, and architecture
  • Collaborate with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects
  • Provide technical guidance and mentorship to team members
  • Oversee the development and implementation of physical design flows and methodologies
  • Collaborate with cross-functional teams to address design challenges and optimize for manufacturability
  • Monitor progress, identify risks, and implement mitigation strategies
  • Keep abreast of the latest industry trends, tools, and techniques in physical design
  • Fulltime
Read More
Arrow Right

Principal Logic Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Raleigh
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Job Responsibility
Job Responsibility
  • Establish yourself as an integral member of a digital logic design team for the development of AI components with focus on micro-architectural based functions and features
  • Be responsible for the logic design/Register Transfer Level (RTL) entry, design quality including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc., and timing closure of high-performance digital IP
  • Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent
  • Interface with physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design
  • Provide technical leadership through mentorship and strong teamwork
  • Fulltime
Read More
Arrow Right

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's or master’s in electrical or computer engineering or related field with 15+ years of experience
  • Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
  • Experience in tapeouts of complex ASICs in leading edge technology
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Job Responsibility
Job Responsibility
  • Lead a team in defining implementation and execution plan for a schip/SOC
  • Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
  • Drive the to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
  • Optimizing technology, libraries, physical design, RTL design, and architecture
  • Leading the team in defining the implementation and execution plan for a subchip/SOC
  • Collaborating with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects to ensure a cohesive plan
  • Executing the defined plan to ensure successful tapeout of the subchip/SOC
  • Driving the team to achieve the best performance, power, and area (PPA) for AI system-on-chips
  • Optimizing technology choices, libraries, physical design methodologies, RTL design strategies, and architectural decisions to meet performance targets
  • Ensuring that the physical design aspects align with the overall project goals and timelines
  • Fulltime
Read More
Arrow Right
New

Onsite Endoscopic Specialist

At KARL STORZ, we are driven by a mission to enhance global health through innov...
Location
Location
United States , Arlington
Salary
Salary:
Not provided
karlstorz.com Logo
KARL STORZ
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • A minimum of high school diploma or equivalent
  • Experience in Sterile Processing, Sales, or other Surgical Technology/Medical role
  • Our successful candidate will have excellent written and spoken English language business communication skills. They will also have demonstrated success working in a collaborative, service-oriented team environment.
  • Effective communicator, collaborative, and effective time management
  • Possess exceptional organizational skills and the ability to multi-task
  • MS Office - proficient user as the role will need to work with Excel spreadsheets and reporting
  • Role requires the completion of a drug screening for safety-sensitive positions
  • Must be able to lift/push/pull up to 25lbs
Job Responsibility
Job Responsibility
  • Face-to-face customer support, including OR, SPD and Biomed
  • Video tower/system set-up and support
  • Inspection, repair, troubleshooting and replacement of KARL STORZ devices
  • Monitoring, reporting, and facilitating repair/ exchange transactions
  • Transporting, cleaning/sterilization and packaging of instruments after use
  • Trouble shoot video and instrument issues in the O.R.
  • Instrument/equipment repair management
What we offer
What we offer
  • Relocation Support
  • Professional Growth & Development
  • Collaborative & Dynamic Work Environment
  • Access to Cutting-Edge Medical Technologies
  • Medical / Dental / Vision including a state-of-the-art wellness program and pet insurance, too
  • 3 weeks vacation, 11 holidays plus paid sick time
  • Up to 8 weeks of 100% paid company parental leave
  • 401(k) retirement savings plan providing a match of 60% of the employee’s first 6% contribution (up to IRS limits)
  • Section 125 Flexible Spending Accounts
  • Life, STD, LTD & LTC Insurance
  • Fulltime
Read More
Arrow Right
New

Pharmacy Technician

We’re building a world of health around every individual — shaping a more connec...
Location
Location
United States , Columbus
Salary
Salary:
17.00 USD / Hour
https://www.cvshealth.com/ Logo
CVS Health
Expiration Date
July 11, 2026
Flip Icon
Requirements
Requirements
  • Must comply with any state board of pharmacy requirements or laws governing the practice of pharmacy, which includes but is not limited to, age, education, and licensure/certification
  • If the state board of pharmacy does not address or mandate a minimum age requirement, must be at least 16 years of age
  • If the state board of pharmacy does not address or mandate a minimum educational requirement, must have a high school diploma or equivalent, or be actively enrolled in high school or high school equivalency program
Job Responsibility
Job Responsibility
  • Living our purpose by following all company SOPs at each workstation to help our Pharmacists manage and improve patient health
  • Following pharmacy workflow procedures at each pharmacy workstation (i.e., production, pick-up, drive-thru, and drop-off) for safe and accurate prescription fulfillment
  • Contributing to positive patient experiences by showing empathy and genuine care: creating heartfelt and personalized moments while serving patients at pick-up, drive-thru, and over the phone
  • keeping patients healthy by offering immunizations and other services at the register and over the phone
  • and demonstrating compassionate care by solving or escalating patient problems
  • Completing basic inventory activities, as permitted by law, and as directed by the pharmacy leadership team, such as accurately putting away medication deliveries and completing cycle counts, returns-to-stocks, waiting bin inventories, etc.
  • Contributing to a high-performing team, embracing a growth mindset, and being receptive to feedback
  • actively seeking opportunities to expand clinical and technical knowledge needed to better assist patients
  • Remaining flexible for both scheduling and business needs, while contributing to a safe, inclusive, and engaging team dynamic
  • voluntarily traveling to stores in the market to work shifts as needed by the business
What we offer
What we offer
  • dental
  • vision
  • wellness resources
  • employee discounts
  • access to certain voluntary benefits
  • other programs
  • Parttime
Read More
Arrow Right