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Microsoft’s Azure Hardware Systems and Infrastructure team builds silicon platforms that power hyperscale cloud and AI workloads. Within the Silicon Engineering organization, this role represents the highest level of technical ownership for timing construction, margining, and end-to-end signoff across advanced SoCs and heterogeneous integrations. As a Principal E2E Timing, Construction & Signoff Engineer, you will define and own timing construction methodologies, uncertainty and margin frameworks, and full-chip signoff strategy across advanced nodes, multi-die systems, and emerging 2.5D/3DIC architectures. This role spans device physics through SoC and system-level convergence and serves as a company-level technical authority, influencing architecture, CAD infrastructure, and foundry-aligned execution.
Job Responsibility:
Own end-to-end timing construction from architecture through block, subsystem, full-chip, and multi-die system signoff
Define uncertainty decomposition, margin budgeting, and guard-banding strategies across clocks, data paths, voltage domains, and operating modes
Act as final technical authority for timing signoff readiness, risk assessment, and tapeout decisions
Define and drive STA methodologies using OCV, POCV, AOCV, SOCV, LVF, and advanced derate models
Align Microsoft signoff practices with foundry-qualified reference flows (TSMC, Samsung, Intel)
Lead hierarchical and context-based STA for large-scale SoCs and chiplet-based systems
Define timing construction methodology for 2.5D/3DIC systems, including die-to-die interfaces, interposers, bridges, micro-bumps, and hybrid bonding
Drive PnR–STA–extraction correlation and resolve RC, waveform, parasitic, and modeling mismatches
Architect scalable Tcl- and Python-based STA infrastructure for central runs, ECO automation, and signoff QA
Influence internal CAD standards and EDA vendor roadmaps through deep technical engagement
Mentor senior engineers and establish org-wide best practices for timing construction and signoff
Perform in-depth root-cause analysis, issue debug and qualification for Microsoft’s broad Silicon portfolio
Collaborate with EDA partners to determine/drive optimal and cutting-edge solutions for effective & efficient CAD solutions
Requirements:
12+ years of industry experience in STA, timing construction, signoff methodology, and PD CAD for large and complex SoCs
Proven ownership of full-chip timing signoff and construction at advanced technology nodes (≤5nm preferred)
Expert-level hands-on experience with PrimeTime and/or Tempus in production signoff environments
Deep understanding of timing construction, margin budgeting, uncertainty modeling, and guard-banding strategies
Strong experience correlating STA with PnR timing engines, extraction, and circuit-level behavior
Advanced Tcl & Python scripting skills for building and maintaining production-quality EDA flows and infrastructure
Ability to meet Microsoft, customer and/or government security screening requirements
Nice to have:
Masters or PhD in Electrical Engineering, Computer Engineering, or related field with VLSI specialization
Hands-on experience with 2.5D/3DIC, chiplets, and advanced packaging timing challenges
Knowledge of aging mechanisms (BTI/HCI), reliability corners, and lifetime margining strategies
Circuit-level understanding of PLL behavior, clock jitter decomposition, and noise-induced timing variation
Strong Python scripting skills for automation, data mining, and signoff analytics
Experience working across multiple foundries and EDA vendors at methodology or reference-flow level