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Principal Design Verification Engineer

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Microsoft Corporation

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Location:
United States , Raleigh

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Contract Type:
Not provided

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Salary:

139900.00 - 274800.00 USD / Year

Job Description:

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Verification & Validation team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Design Verification Engineer to join the team.

Job Responsibility:

  • Own or lead verification of complex flows at Fabric Interconnect or at block level
  • Learn about the design and interact with partner teams to define verification strategies and test plans
  • Develop UVM-based verification environments and run and debug simulations to drive quality
  • Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
  • Innovate to improve verification efficiency through methodologies or tools
  • Apply industry leading generative AI solutions to verification work
  • Coach and mentor others in your areas of expertise
  • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Requirements:

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • Provide proof of citizenship or US residency/protected status for export control assessment
  • 5+ years of pre-silicon subsystem or IP verification experience
  • Demonstrated expertise in leading verification of designs that utilize Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols
  • Demonstrated expertise in one or more of the following: fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and/or protocol bridges
  • Experience driving IP verification for multiple product cycles from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff
  • Demonstrated hands-on technical leadership such as creating bottom’s up schedules, coordinating work across a team, driving verification closure, or solving cross-team technical problems
  • Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking
  • Aptitude for writing scripts/software with industry standard languages like Python
  • Experience applying generative AI to day-to-day tasks

Additional Information:

Job Posted:
March 04, 2026

Employment Type:
Fulltime
Work Type:
Hybrid work
Job Link Share:

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