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Principal Design Engineer

https://www.microsoft.com/ Logo

Microsoft Corporation

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Location:
United States , Mountain View

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Contract Type:
Not provided

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Salary:

139900.00 - 274800.00 USD / Year

Job Description:

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the SCHIE team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Design Engineer with expertise in SoC level Power Optimization to join the AI SoC Design team which is an integral Part of SCHIE. This team is responsible for all the AI accelerator silicon designs. An ideal candidate should have high level of expertise in techniques of power optimizations, Power projection Tools and methodologies and breadth of knowledge in the areas of micro-architecture, Logic and Physical designs. Expertise in the areas of SRAM and register-file designs, memory compiler usages, interconnect and clock designs are highly desirable.

Job Responsibility:

  • Work with the architecture and micro-architecture leads to identify and propose new Power Optimization ideas and trade-offs
  • Prepare input collaterals including appropriate Logic stimuli for Prime Power RTL and PTPX PD flows
  • Collaborate with central Flow/methodology team to pilot new power flows
  • Power-performance analysis
  • Roll up SoC level Power models
  • Generate Thermal maps
  • Project power for future generation of SoC based on architecture changes and appropriate scaling techniques from the past projects across different technology nodes
  • Define Voltage and frequency targets to fit Power budgets
  • Influence designs in the areas of Logic memories, interconnects and clocking for optimal SoC power.

Requirements:

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • Over 5+ years of experience in the area of Power analysis and Low power optimization
  • Over 5+ years of experience in the areas of micro-architecture or Logic and/or SRAM register-file, Clocking
  • Experience with Front-end and Back-end Power analysis tools like Power Artist, RTLA, PTPX etc.

Additional Information:

Job Posted:
February 01, 2026

Employment Type:
Fulltime
Work Type:
On-site work
Job Link Share:

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