Power Methodology Engineer, Data Center Hardware IPs Job at AMD (Santa Clara)

Job Description

A senior power lead for power architecture solutions, specializing in areas like microprocessors, GPUs, and machine learning accelerators to optimize power efficiency and performance. This involves creating power management algorithms, developing power models, and collaborating with cross-functional teams to implement and validate power-saving features throughout the design cycle

Job Responsibility

Focuses on optimizing the energy efficiency and power delivery of high-performance computing hardware used in large-scale AI and machine learning applications
Driving power methodology for AI-specific hardware components (like tensor cores and matrix multiplication engines) and using simulation tools (e.g., PowerArtist, PTPX) to estimate and optimize power consumption
Workload Optimization: Analyze the power and performance characteristics of AI, Graphics, Battery life WLs, especially specific WLs for NPUs, GPUs, and CPUs
Performance/Watt Optimization: Focus on maximizing performance while staying within strict power and thermal limits, which is critical for both data center and gaming applications
Power Optimization: Estimate and analyze power consumption at various stages of chip design (architecture, RTL, physical design)
Analysis and modeling: Creating power models and scripts for performance/power trade-offs
Methodology Development: Researching, developing, and deploying methodologies and automated flows (using scripting languages like Python or Perl) to enhance power analysis efficiency
Collaboration: Working with other teams, including RTL, Architecture, Physical Design, Emulation, software, Firmware to ensure power requirements are met across the hardware-software stack
Leadership: Mentoring junior team members and providing technical leadership on complex projects

Requirements

Extensive industry experience, with a specialization in low-power-processor architectures or power management
Expertise in ASIC/SoC power analysis and optimization techniques
Working experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design)
AI/ML Concepts: Familiarity with machine learning algorithms and their application to power simulation/optimization, as well as an understanding of NPU function and AI workload characteristics
Proficiency in hardware description languages like Verilog or VHDL, and scripting
Strong analytical skills and experience with power analysis tools (e.g., PowerArtist, PTPX)
Expertise in hardware description languages (Verilog, VHDL), scripting (Python), and simulation/analysis tools
Strong analytical and problem-solving skills to tackle complex, multidisciplinary power and performance challenges
Several years of experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design)
Strong scripting and automation skills, preferably in Python
Excellent communication, presentation, and leadership skills to drive projects and collaborate effectively with cross-functional teams
Master's degree or PhD in a relevant field, such as Electrical or Computer Engineering, is often preferred

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Power Methodology Engineer, Data Center Hardware IPs

Job Description

Job Responsibility

Requirements

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