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This role focuses on validating end‑to‑end system behavior, ensuring that multiple SoC subsystems interact correctly under real customer and system‑level use cases.
Job Responsibility:
Own SoC‑level post‑silicon validation, focusing on interaction between multiple subsystems rather than isolated IP testing
Validate end‑to‑end system flows involving CPU cores, on‑chip memories, NoC/interconnect, IOs, power management, and firmware
Ensure correct behavior across boot, runtime, stress, error, and recovery scenarios at the SoC level
Develop validation test cases based on customer use cases (boot flows, IO usage, stress, concurrency, power transitions) into executable validation plans
Debug & root cause analysis: Perform deep SoC‑level debug to isolate failures across hardware, firmware, and system software boundaries
Lab execution & characterization: Use engineering lab equipment (oscilloscopes, protocol analyzers, signal generators, etc.) to validate and debug functional behavior
Documentation & reporting: Produce clear test plans, execution reports, failure analysis summaries, and status updates
track bugs/issues to closure
Requirements:
12+ years of experience in pre‑silicon and/or post‑silicon SoC validation, with strong ownership in post‑silicon execution
Strong understanding of SoC architecture and subsystem interactions
Experience validating system‑level use cases and customer‑driven scenarios
Familiarity with debug tools, system logs, traces, and lab‑based validation setups
Strong understanding of SoC boot flows, firmware, and HW/SW interaction
Lab proficiency: Extensive experience using lab equipment such as oscilloscopes, protocol analyzers, signal generators, etc.
Nice to have:
Experience with emulation platforms (Palladium, Protium, Zebu) for pre‑silicon or early validation
Exposure to NoC fabrics, power management, clock/reset architecture, and system controllers
Familiarity with system software stacks (bootloader, Linux, RTOS) and their interaction with silicon