Post Silicon Power and Performance Staff Engineer Job at AMD (Penang)

Senior Member of Technical Staff (MTS) – Post‑Silicon SoC & System‑Level Validation Engineer

This role focuses on validating end‑to‑end system behavior, ensuring that multip...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

12+ years of experience in pre‑silicon and/or post‑silicon SoC validation, with strong ownership in post‑silicon execution
Strong understanding of SoC architecture and subsystem interactions
Experience validating system‑level use cases and customer‑driven scenarios
Familiarity with debug tools, system logs, traces, and lab‑based validation setups
Strong understanding of SoC boot flows, firmware, and HW/SW interaction
Lab proficiency: Extensive experience using lab equipment such as oscilloscopes, protocol analyzers, signal generators, etc.

Job Responsibility

Own SoC‑level post‑silicon validation, focusing on interaction between multiple subsystems rather than isolated IP testing
Validate end‑to‑end system flows involving CPU cores, on‑chip memories, NoC/interconnect, IOs, power management, and firmware
Ensure correct behavior across boot, runtime, stress, error, and recovery scenarios at the SoC level
Develop validation test cases based on customer use cases (boot flows, IO usage, stress, concurrency, power transitions) into executable validation plans
Debug & root cause analysis: Perform deep SoC‑level debug to isolate failures across hardware, firmware, and system software boundaries
Lab execution & characterization: Use engineering lab equipment (oscilloscopes, protocol analyzers, signal generators, etc.) to validate and debug functional behavior
Documentation & reporting: Produce clear test plans, execution reports, failure analysis summaries, and status updates
track bugs/issues to closure

What we offer

AMD benefits at a glance

Fulltime

Staff Engineer, ASIC development Engineering

As a SoC Validation/Verification Engineer, you will play a key role in ensuring ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BE or MS degree in Electrical Engineering or Computer Engineering
5-8+ years of experience in SoC pre-/post-silicon verification and validation, and bring-up
Deep understanding of C, embedded programming, and hardware/software co-validation methodologies
Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts
Proven history of developing and executing verification and validation strategies for complex SoCs
Experience in verification and validation of industry-standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, AXI, AHB, and APB
Must understand and contribute to complex SoC-level testbenches, including UVM, C, and SystemVerilog components
Strong experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug for both pre- and post-silicon phases
Hands-on experience in post-silicon ASIC bring-up, validation, and debug
Should have a very good understanding of C, Python, or Perl scripting languages for test automation, data analysis, and tool development

Job Responsibility

Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre- and post-silicon validation
Independently developing and executing tests for verification and validation
Collaborating with cross-functional teams to drive closure of verification and validation activities
Signing off on verification and validation deliverables
Debugging and root cause analysis of issues found during validation
Developing and maintaining automated test environments and regression suites
Contributing to the continuous improvement of verification methodologies and best practices
End-to-end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure
Run complex SoC verification and validation scenarios on Palladium/Emulation platforms to accelerate debug and improve pre-silicon coverage
Execute verification and validation cases in simulation environments and perform initial debug and root cause analysis

Fulltime

Non-Volatile Memory (NVM) Design Engineer, Staff

Synopsys software engineers are key enablers in the world of Electronic Design A...

Location

Taiwan , Hsinchu

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

5–12+ years of industry experience in circuit design, with a strong emphasis on analog circuit design and analysis
memory design experience is a significant plus
Deep understanding of layout considerations for advanced nodes, including parasitic effects, matching techniques, and signal integrity
Expertise in electrical problem-solving, including root cause analysis of circuit failures and development of effective solutions
Hands-on experience with TestChip tapeout flows, silicon debugging (FIB, micro-probing, post-layout RC extraction), and statistical design methodologies (e.g., Monte-Carlo analysis)
Strong transistor-level analog design skills, including sense-amplifier, charge pump, high voltage regulator, and bandgap reference circuit design
Proficiency with circuit simulation tools (HSIM, HSPICE, etc.) and custom schematic/layout editors (e.g., Custom Compiler)
Experience with low power design, power management circuitry, and FinFET design is a plus
A collaborative team player who thrives in multicultural, cross-functional teams
Independent, self-motivated, and able to manage multiple priorities in a fast-paced environment

Job Responsibility

Leading the NVM TestChip and IP design flow across multiple technologies and foundries, ensuring robust and scalable solutions for diverse applications
Architecting, designing, and verifying CMOS-based non-volatile memory IP modules, from concept to production tapeout
Collaborating with product engineers to perform silicon verification, in-depth testing, and debugging to validate IP performance on silicon
Conducting post-layout extraction, simulation, and comprehensive testing in conjunction with silicon validation teams
Working closely with on-site and off-site design, layout, and CAD teams to optimize design methodologies and ensure project success
Partnering with layout designers on floor planning of memory arrays and analog blocks for performance, area, and manufacturability optimization
Serving as the technical expert to support Sales and Application Engineers during complex pre- and post-sales customer engagements, ensuring customer satisfaction and successful product adoption

What we offer

Comprehensive medical and healthcare plans that work for you and your family
In addition to company holidays, we have ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

Analog Design, Staff Engineer

In this role, you will work on the design, development, and refinement of Multi-...

Location

Canada , Ottawa

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

Ph.D., M.Sc. with 3+ years, or B.Sc. with 5+ years of practical analog IC design experience
degree in Electrical Engineering or Computer Engineering or other relevant field of study
In depth familiarity with transistor level circuit design - sound CMOS design fundamentals
Detailed design experience with one, and familiarity with several other SERDES sub-circuits: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC
Familiarity with custom digital design (i.e. high-speed logic paths)
Experience with analog/digital interactions for optimizing circuit performance (calibration, adaptation, timing-handoff, etc)
Understanding of design for reliability (i.e. EM, IR, aging, etc.) and layout effects (i.e. matching, reliability, proximity effects, etc.) as well as ESD issues (i.e. circuit techniques, layout)
Experience with tools for schematic entry, physical layout, and design verification
Understanding of SPICE simulators and simulation methods
Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture

Job Responsibility

Review SERDES standards to develop novel transceiver architectures and sub-block specifications
Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area, and performance targets
Oversee physical layout to minimize the effect of parasitics, device stress, and process variation
Present and review simulation data from internal project teams
Document design features and test plans
Consult on the overall electrical characterization of the SERDES IP product. Review customer silicon data for design enhancements. Propose solutions for post-silicon design updates

What we offer

Comprehensive medical and healthcare plans
Time Away in addition to company holidays, ETO and FTO Programs
Family Support including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
ESPP - Purchase Synopsys common stock at a 15% discount
Retirement Plans
Competitive salaries

Fulltime

Staff Verification Engineer

We are looking for an experienced Verification Engineer to join our team for cut...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in related discipline
Advanced knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl
Developed and implemented SystemVerilog and UVM based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems
Worked closely with hardware, firmware, and software teams to align on system-level memory architecture, identify potential integration issues, and define validation requirements early in the design phase
Built VIPs and BFMs for memory interfaces from scratch (preferrable)
GLS, NLP, XPROP simulation experience is preferable
Strong proficiency in system verilog assertions, constraints and coverage
Worked in formal verification methods, with proven record of tool usage beyond the standard apps
Excellent communication, management, and presentation skills

Job Responsibility

Work with a team verification engineers in the development and execution of verification plan for DDR5, LPDDR5, and DFI memory systems in server products
Comprehend the PHY's interaction in the complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface
Understand RTL and micro-architecture sufficiently to engage in cross functional discussions with IP/Domain architects and Design engineers for planning and debug
Knowledge sharing and other contributions to verification methodology
Support Post-Si teams for Product Performance, Power and functional issues debug/resolution

Staff Product Development Engineer

We are the high-end test engineering team providing test solutions for Data Cent...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Knowledge or hands-on working experience
Good understanding of power and performance characterization on ATE
ATE Test handling/ execution and development experience - Advantest V93K experience preferred. (Advantest SMT8 experience is a plus)
Software programming and scripting proficiency (C++, Java, Groovy, Perl, Ruby, Python)
Proficiency in Windows and Linux operating systems
Experience with HVM (High Volume Manufacturing) is a strong plus
Strong and effective presentation, written and verbal communication skills, and the ability to work with geographically distributed product engineering teams
Excellent interpersonal, organizational, and analytical skills
8 years or more of industry experience
Electrical/Electronics, Computer Engineering, or comparable disciplines

Job Responsibility

Accountable to drive test solution/coverage development, optimization to meet business milestone, cost and quality
Test patterns & test flows/method development, debug, test and characterization
Pre-Silicon engagement with Design, test solution/methodology scoping, planning & validation
Post Silicon Bring up of test patterns leading to optimization for mass production enablement
Characterization execution/analysis and debug of new silicon designs and process technologies
Optimization of test coverage and flows for increased quality, yield, cost improvement, and test time reduction
Conduct engineering evaluations and analysis to drive closure of production issues
Solves complex, novel, and non-recurring problems
initiate significant changes to existing processes/methods and leads development and implementation
Influences technical decisions that have a significant impact on final product

What we offer

AMD benefits at a glance

Fulltime

Senior Staff Physical Design Engineer

We are looking for an adaptive, self-motivative physical design engineer to join...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience and specialization in deep‑submicron ASIC physical design, including all phases from RTL-to-GDSII and signoff
Proven record of Physical Design signoff flow
Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Tempus, PrimeTime, Fusion Compiler, Calibre)
Excellent scripting skills in TCL, Shell, Python, or Perl to enhance PD flows and automation
Proven ability to work with cross-functional teams across multiple sites/time zones
Strong analytical, problem-solving, and communication skills
Familiarity with CPU and or GPU architecture
Proficiency in data analysis and interpretation

Job Responsibility

Static Timing Analysis (STA) across MMMC scenarios: Driving timing closure at block and full‑chip levels, resolving violations through ECOs, constraint refinements, and reviewing SoC and block‑level signoff readiness. Lead timing signoff (setup, hold, OCV, AOCV/POCV, SI, CDC interfaces) across all modes and corners
Logic Equivalence Check (LEC) for all blocks and full‑chip: Executing equivalence verification between RTL, synthesis, and P&R databases
Low‑power structural checks (UPF/CLP): Ensuring correctness of power‑intent implementation, power‑domain crossings, isolation/retention, and coverage of low‑power signoff flows
Physical Integrity Signoff: Overseeing DRC/LVS structural verifications, and ensuring designs adhere to foundry signoff rules. Perform and review IR drop, EM, and power integrity signoff
Clocking and top‑level mesh implementation and signoff
Own and drive block-level and/or full-chip physical implementation and signoff to tape-out
Analyze complex cross-block and top-level signoff issues and define closure strategy
Define and enforce signoff criteria, methodologies, and best practices
Partner with PD implementation teams to guide ECO strategy for timing, power, and physical fixes
Identify risk areas early and proactively drive mitigation plans

Staff Product Development Engineer - ATE Test Solutions

We are the high-end test engineering team providing test solutions for Data Cent...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proficient understanding of DFT(Design-For-Test) architecture for SOC (System-On-Chip) product
Strong test development, Silicon characterization/debug working experience with various industry standard ATE test platforms
Data analysis
Knowledge or hands-on working experience
Good understanding of power and performance characterization on ATE
ATE Test handling/execution and development experience - Advantest V93K experience preferred (Advantest SMT8 experience is a plus)
Software programming and scripting proficiency (C++, Java, Groovy, Perl, Ruby, Python)
Proficiency in Windows and Linux operating systems
Experience with HVM (High Volume Manufacturing) is a strong plus
Strong and effective presentation, written and verbal communication skills

Job Responsibility

Accountable to drive test solution/coverage development, optimization to meet business milestone, cost and quality
Test patterns & test flows/method development, debug, test and characterization
Pre-Silicon engagement with Design, test solution/methodology scoping, planning & validation
Post Silicon Bring up of test patterns leading to optimization for mass production enablement
Characterization execution/analysis and debug of new silicon designs and process technologies
Optimization of test coverage and flows for increased quality, yield, cost improvement, and test time reduction
Conduct engineering evaluations and analysis to drive closure of production issues
Solves complex, novel, and non-recurring problems
initiate significant changes to existing processes/methods and leads development and implementation
Influences technical decisions that have a significant impact on final product

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Post Silicon Power and Performance Staff Engineer

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