Pmts Silicon Design Engineer Job at AMD (Hyderabad)

Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. We are seeking a senior technical leader to serve as the Chief Engineer ensuring AI‑augmented Physical Design (PD) continues to operate with world‑class engineering rigor. This role sits at the intersection of RTL design, microarchitecture ownership, and Physical Design, with a mandate to shift left PD risk, enforce execution quality, and provide engineering judgment as AI and automation increasingly drive RTL‑to‑GDS flows.

Job Responsibility

Own Physical Design shift‑left strategy, ensuring PD risks are identified at RTL, SDC, and paper‑floorplan stages
Act as chief engineering authority for AI‑assisted and automated PD execution, defining where AI can act autonomously and where human judgment is required
Bridge RTL, microarchitecture, and PD, translating early PD findings into architectural and RTL‑level corrective actions
Define and enforce PD readiness and quality bars across synthesis, PnR, STA, and physical closure
Lead predictive closure and risk management, using early indicators to forecast timing, ECO churn, and execution complexity
Govern signoff readiness, ensuring AI‑augmented flows never compromise correctness or confidence
Codify execution playbooks and best practices to reduce variability and scale high‑quality PD execution across teams
Serve as a trusted technical peer to RTL architects, PD leads, and AI/methodology owners

Requirements

14–18+ years of semiconductor design experience
Strong hands‑on RTL design and microarchitecture ownership, with designs that progressed through PD and tapeout
Direct experience working within or closely alongside Physical Design teams
Deep understanding of SDC intent, timing, clocking, partitioning, and physical closure trade‑offs
Proven ability to resolve PD issues through architectural and RTL‑level solutions, not late physical workarounds
Experience driving or contributing to shift‑left initiatives or early physical feasibility analysis
Comfort operating as a senior technical authority, making cross‑domain engineering decisions
Exposure to AI‑assisted or highly automated design flows is a strong plus
Own creation and maintenance of physical‑aware RTL to enable PNR hierarchy, including partitioning, feedthroughs, repeaters, and physical intent insertion
Partner with SOC Design to translate logical IP integration into physical‑aware RTL and with IP design team creation digital‑on‑top RTL wrappers for analog IPs
Must be fluent in physical implementation aspects of functional integration protocols - AXI / APB , NoC , Memory (DDR/HBM) , Coherency, Interrupt/Debug , DFX protocols (iJTAG, BSCAN etc), Clocking and reset logic
Bachelor’s or Master’s degree in related discipline preferred

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Pmts Silicon Design Engineer

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