Physical Design Lead - CPU Team Job at AMD (Bangalore)

CPU Physical Design Lead

The position will involve working with a very experienced CPU physical design te...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

8+ years of professional experience in physical design, preferably with high-performance designs
Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc.
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality
familiarity with tools for schematics, layout, and circuit/logic simulation
Versatility with scripts to automate design flow - Perl/Tcl/Python
Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
Experience in advanced sub 7nm nodes
Excellent physical design and timing background
A good understanding of computer architecture is preferred
Strong analytical/problem-solving skills and pronounced attention to detail

Job Responsibility

Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff
Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure
Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA
Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff
Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk

Lead Soc Physical Design Engineer

As a member of the Strategic Silicon Solution Group Full Chip Physical Design te...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Minimum 15+ years of relevant work experience
Expertise in ICC2/FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools
Expertise in Signoff tools like Primetime for Timing, Calibre for DRC/LVS, Ansys Redhawk on EMIR, PT-PX for Power signoff
Should have worked as a go to person or technical lead for at least few full chip projects
Strong technical leadership and ability to mentor/guide/coach design engineers
Strong inter-personal skills and ability to collaborate with teams spread across multiple geos
Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts
Bachelors or Master's degree in Computer/Electronics/Electrical Engineering
Experience in 5nm & below technologies
Hands-on in reference flows, excellent debugging skills

Job Responsibility

Full chip level Die size estimation, Floor-planning, Power planning, IO planning, package compatibility, IO ring creation and ESD analysis
Full chip Hierarchical planning, block planning , block level constraints, hierarchical clock tree implementation, block integration and chip finishing
Low power design with power estimation/optimization including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption
Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPF
Full chip / sub-system level constraints, MMMC & cross talk aware timing closure with latest OCV based analysis
RTL2GDSII design implementation and flow debug top down or bottoms up at chip level
PPA (Power, Performance, Area and Schedule) closure and flow development for key IPs like CPU, Graphics, Multimedia, Fabric cores and/or other critical sub-systems
Low Power signoff like Static and Dynamic power analysis at top level and/or sub-system level
Full chip / sub system level Clock tree synthesis and advanced clock tree implementation
Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion and logic equivalence

Senior RTL Design Lead

We are seeking a seasoned Principal design engineer with expertise or significan...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Excellent foundation in fabric/transport architecture and coherency
Experience in memory design/cache design
Bachelor’s or Master’s degree in computer engineering/Electrical Engineering
Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security
Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads
Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
Excellent communication, management, and presentation skills
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

Job Responsibility

Define Data Fabric features and capabilities required to meet SoC requirements on power, performance, Area targets
Digital design implementation and micro-architecture of components of the Infinity Data Fabric, including cache design
Micro-architecture and RTL coding in Verilog/SystemVerilog
Lead design on one or more domains
Work with architects and design leads to identify and assess complex technical issues
Work closely with verification teams to ensure quality component development
Work closely with Physical design to ensure quality PPA targets
Post silicon support to ensure successful bring up
Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams
Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power

Senior Staff Physical Design Engineer

We are looking for an adaptive, self-motivative physical design engineer to join...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience and specialization in deep‑submicron ASIC physical design, including all phases from RTL-to-GDSII and signoff
Proven record of Physical Design signoff flow
Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Tempus, PrimeTime, Fusion Compiler, Calibre)
Excellent scripting skills in TCL, Shell, Python, or Perl to enhance PD flows and automation
Proven ability to work with cross-functional teams across multiple sites/time zones
Strong analytical, problem-solving, and communication skills
Familiarity with CPU and or GPU architecture
Proficiency in data analysis and interpretation

Job Responsibility

Static Timing Analysis (STA) across MMMC scenarios: Driving timing closure at block and full‑chip levels, resolving violations through ECOs, constraint refinements, and reviewing SoC and block‑level signoff readiness. Lead timing signoff (setup, hold, OCV, AOCV/POCV, SI, CDC interfaces) across all modes and corners
Logic Equivalence Check (LEC) for all blocks and full‑chip: Executing equivalence verification between RTL, synthesis, and P&R databases
Low‑power structural checks (UPF/CLP): Ensuring correctness of power‑intent implementation, power‑domain crossings, isolation/retention, and coverage of low‑power signoff flows
Physical Integrity Signoff: Overseeing DRC/LVS structural verifications, and ensuring designs adhere to foundry signoff rules. Perform and review IR drop, EM, and power integrity signoff
Clocking and top‑level mesh implementation and signoff
Own and drive block-level and/or full-chip physical implementation and signoff to tape-out
Analyze complex cross-block and top-level signoff issues and define closure strategy
Define and enforce signoff criteria, methodologies, and best practices
Partner with PD implementation teams to guide ECO strategy for timing, power, and physical fixes
Identify risk areas early and proactively drive mitigation plans

Ip Post-Silicon Validation Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great pro...

Location

Canada , Markham

Salary:

155200.00 - 232800.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Bachelor's or master’s degree majoring in EE, CS or related field
Experience in digital logic design/verification/post-silicon validation
Extensive experience with ASIC debug techniques and methodologies
Knowledge of physical and protocol levels of common high-speed interfaces such as PCIe/CXL/UALINK is an asset
Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization
Strong scripting skills (eg. Ruby, Python)
Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
In-depth knowledge of PC architectures/PCIe protocol is an asset
Must have excellent written and verbal communication skills
Must excel in a dynamic team working environment

Job Responsibility

Driving the planning, validation, and debug of various hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs
Defining, documenting, executing and reporting the overall functional test plan and validation strategy for a set of AMD IP’s
Driving technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts/automation development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives
Debugging IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs
Engaging on pre-silicon ‘shift left’ activities with cross-functional teams such as Design Verification (DV), Diagnostics, Emulation and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features
Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives
Developing knowledge of system architecture/debug and other internal IP’s
Supporting issues on customer platforms as requested by customer support teams

Fulltime

Business Development Sr. Manager

The Business Development Senior Manager entails responsibilities for working wit...

Location

United States , Santa Clara

Salary:

186720.00 - 280080.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Progressive datacenter experience, with a strong record across key verticals
Strong historical relationships and engagement within the semiconductor industry
Strong understanding of enterprise technology adoption and vertical-specific business models
Able to operate effectively in fast-moving, cross-functional environments
Excellent communication, storytelling, and executive-level presentation skills
Familiarity with AI/ML stacks, enterprise software, and industry-specific digital transformation is a plus
Undergraduate degree in Electrical Engineering, Computer Science, or Computational Sciences preferred. MBA is a plus

Job Responsibility

Define and implement strategies to grow AMD's server business in the Semiconductor/EDA vertical through a solutions-based approach spanning CPU, GPU, and software
Conduct competitive, market, and partner capability assessments to shape actionable vertical expansion plans, and build the frameworks (market analysis, vendor evaluation, business case, partnership execution) that support them
Build and convert the Semiconductor/EDA pipeline through deep partnerships with semiconductor companies, foundries, EDA vendors (e.g., Synopsys, Cadence, Siemens EDA, Ansys), and ecosystem partners
Develop solution sets tied to key EDA and CAE workloads (e.g., RTL/logic simulation, physical verification, place-and-route, static timing analysis, DRC/LVS, SPICE, emulation, AI/ML-driven chip design), with joint value propositions and go-to-market plans to accelerate growth
Lead development of vertical-specific AI solutions in collaboration with ecosystem partners
Incubate POCs and pilots by orchestrating product, engineering, sales, and marketing teams, and turn them into scalable, repeatable offers with reference architectures and supporting collateral
Partner with server OEMs, the server systems channel, GSIs, and CSPs to converge on solutions addressing end-customer needs across on-prem, cloud, and hybrid deployments
Enable sales and marketing with targeted plays, collateral, and training
build cross-sales relationships to drive a unified approach in key Semiconductor/EDA accounts
Translate customer challenges into compelling value propositions that connect chip-level technology to system-level solutions

Fulltime

Cpu Power Estimation And Optimization

WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great pro...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Deep expertise in CPU micro-architecture and power drivers
Strong background in power modeling, estimation, and correlation for high-performance CPUs
Proven ability to influence architecture decisions using quantitative power analysis
Advanced-node CPU design experience
Pre-silicon to post-silicon power correlation experience
Experience defining reusable CPU power methodologies adopted at scale

Job Responsibility

Act as the technical lead for CPU power estimation and optimization, shaping power strategy for high-performance CPU cores
Deliver credible power projections from early architecture through sign-off and influence CPU design decisions across multiple generations
Define CPU power architecture including core, cache (L1/L2/L3)
Establish voltage domains power goals for each states, performance states, low-power modes, and CPU use-case power envelopes
Drive power-performance-area (PPA) tradeoffs for different goals for CPU units
Quantify power cost of CPU micro-architectural features (pipeline depth, width, speculation, cache structures, predictors, queues, buffers)
Evaluate power impact of ISA extensions, frequency targets, and workload characteristics
Use prior-generation CPU data to guide next-generation architectural decisions
Own early CPU power estimation using architecture-level parameters (flops, SRAM bits, activity proxies, frequency, topology)
Define correlation strategy from early estimates to RTL power to physical implementation to silicon

Fulltime

Principal Engineer I – Master Data Management Engineer

Software Resources has an immediate, direct hire job opportunity for a Principal...

Location

United States , Irving

Salary:

Not provided

Software Resources

Expiration Date

Until further notice

Requirements

Must have hands-on experience in Profisee or other MDM tools
C# & .NET are Required
8+ years' experience with MDM solutions using Profisee or any other MDM tools
3+ years' experience designing, implementing, and supporting cloud data solutions
Azure Data Lake Storage, Azure Data Factory, Azure Data Services, Azure Logic Apps etc
Bachelor's degree in related field required
Expert level experience with at least one RDBMS and query language such as T-SQL, PL/SQL, Spark SQL
Expert level experience in conceptual, logical, and physical data design
Advanced to expert knowledge of general Financial Services or Banking is preferred
Advanced to expert knowledge of applicable regulatory and legal compliance obligations, rules and regulations, industry standards, and practices

Job Responsibility

Design, develop, and implement key components of the enterprise data platform
Lead the design, development, and maintenance of MDM solutions using Profisee
Develop and implement data quality rules and processes within Profisee
Design, develop, and implement match and merge functionalities, as well as hierarchical structures, utilizing Profisee
Establish and implement survivorship rules, business rules, and workflow automations
Diagnose and resolve long-running processes, as well as memory and CPU performance concerns
Design and implement Azure DevOps CI/CD pipelines to facilitate the deployment of Profisee deliverables
Design and implement data integration processes between Profisee and other enterprise systems
Participate in the full MDM implementation lifecycle
Collaborate with cross-functional teams and business stakeholders to define master data domains

What we offer

medical
dental
vision coverage
401(k) with company match
short-term disability
life insurance with AD&D

Fulltime

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Physical Design Lead - CPU Team

Job Description

Job Responsibility

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