Physical Design Lead - CPU Team Job at AMD (Bangalore)

CPU Physical Design Lead

The position will involve working with a very experienced CPU physical design te...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

8+ years of professional experience in physical design, preferably with high-performance designs
Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc.
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality
familiarity with tools for schematics, layout, and circuit/logic simulation
Versatility with scripts to automate design flow - Perl/Tcl/Python
Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
Experience in advanced sub 7nm nodes
Excellent physical design and timing background
A good understanding of computer architecture is preferred
Strong analytical/problem-solving skills and pronounced attention to detail

Job Responsibility

Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff
Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure
Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA
Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff
Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk

New

Rtl design lead - cpu team

At AMD, our mission is to build great products that accelerate next-generation c...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

6+ years of experience in Digital IP/ASIC design and Verilog RTL development
Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification
Well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation
Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects
Should possess expertise in front-end EDA tools sign-off and its flows
Familiarity with low power design and low power flow is an added plus
Ability to program with scripting languages such as Python or Perl is a plus
Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements
Proven interpersonal skills, leadership and teamwork
Excellent writing skills in the English language, editing and organizational skills required

Job Responsibility

RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
Architect and design of power management features, cache, coherency
Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
Responsible for the inter IP integration issues resolution
Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem
Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design
Architecting, micro-architecting and documentation of the design features
Lead design team from all aspects of the RTL deliverables
Mentor the junior members of the RTL team to meet the team goals
Represents AMD to the outside technical community, partners and vendors

New

Lead Soc Physical Design Engineer

As a member of the Strategic Silicon Solution Group Full Chip Physical Design te...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Minimum 15+ years of relevant work experience
Expertise in ICC2/FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools
Expertise in Signoff tools like Primetime for Timing, Calibre for DRC/LVS, Ansys Redhawk on EMIR, PT-PX for Power signoff
Should have worked as a go to person or technical lead for at least few full chip projects
Strong technical leadership and ability to mentor/guide/coach design engineers
Strong inter-personal skills and ability to collaborate with teams spread across multiple geos
Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts
Bachelors or Master's degree in Computer/Electronics/Electrical Engineering
Experience in 5nm & below technologies
Hands-on in reference flows, excellent debugging skills

Job Responsibility

Full chip level Die size estimation, Floor-planning, Power planning, IO planning, package compatibility, IO ring creation and ESD analysis
Full chip Hierarchical planning, block planning , block level constraints, hierarchical clock tree implementation, block integration and chip finishing
Low power design with power estimation/optimization including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption
Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPF
Full chip / sub-system level constraints, MMMC & cross talk aware timing closure with latest OCV based analysis
RTL2GDSII design implementation and flow debug top down or bottoms up at chip level
PPA (Power, Performance, Area and Schedule) closure and flow development for key IPs like CPU, Graphics, Multimedia, Fabric cores and/or other critical sub-systems
Low Power signoff like Static and Dynamic power analysis at top level and/or sub-system level
Full chip / sub system level Clock tree synthesis and advanced clock tree implementation
Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion and logic equivalence

New

Senior RTL Design Lead

We are seeking a seasoned Principal design engineer with expertise or significan...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Excellent foundation in fabric/transport architecture and coherency
Experience in memory design/cache design
Bachelor’s or Master’s degree in computer engineering/Electrical Engineering
Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security
Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads
Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
Excellent communication, management, and presentation skills
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

Job Responsibility

Define Data Fabric features and capabilities required to meet SoC requirements on power, performance, Area targets
Digital design implementation and micro-architecture of components of the Infinity Data Fabric, including cache design
Micro-architecture and RTL coding in Verilog/SystemVerilog
Lead design on one or more domains
Work with architects and design leads to identify and assess complex technical issues
Work closely with verification teams to ensure quality component development
Work closely with Physical design to ensure quality PPA targets
Post silicon support to ensure successful bring up
Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams
Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power

Principal Systems Electrical Engineer - AI/Hyperscale Servers

The Senior Staff Electrical Engineer will have demonstrated technical leadership...

Location

United States , Secaucus

Salary:

116250.00 - 193750.00 USD / Year

Sanmina

Expiration Date

Until further notice

Requirements

Bachelor’s Degree in Electrical Engineering
12+ years of experience directly related to the design and debugging of computer-related PCB boards
Skilled in Analog and digital design
Skilled in high-speed bus interface design
Knowledge of high-speed PCB layout design
Strong ability to debug high-speed designs and signal integrity issues
Knowledge of power distribution techniques & x-86 processor system architecture
Ability to implement high-speed serial busses (SAS/SATA, PCIe, USB) and/or high-speed parallel busses (DDR2/3), and CPU front-side bus
Skilled in feature and cost trade-off analysis
Ability to create specifications and design guides

Job Responsibility

Take the lead in interfacing with cross-functional teams to develop system-level architectures and board-level implementations from product early concept through production launch
In charge of preparing specifications, BOM, design, and schematic entry internally and supervising the design work by junior engineers and external suppliers
Make decisions related to layout guidelines for PCBs and supervise Layout Engineers ensuring that all physical and electrical requirements are met
Analyze the design with simulation tools and make calculations to verify its conformance to the design requirements
Lead and mentor layout, system bring-up, and debug teams
Work with suppliers, contractors, and principal design engineers to ensure that the product is developed on time with high quality
Make decisions and specify production test methods and limits
Drive balance between cost, performance, quality, and schedule and supervise international and domestic engineering teams

What we offer

Competitive base salary
Performance-based annual bonus eligibility
401(k) retirement savings plan
Tuition reimbursement for eligible education programs
Comprehensive medical, dental, and vision coverage with access to leading providers
Mental health resources and employee wellness support programs
Company-paid life and disability insurance
Paid time off (PTO) and company-paid holidays
Parental leave and family care support programs
Structured training programs and on-the-job learning opportunities

Fulltime

New

Field Application Engineer - Datacenter

We are looking for our next team member to support this strategic Mega Datacente...

Location

United States , Bellevue

Salary:

203760.00 - 305640.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Excellent interpersonal and communication skills (written, verbal and presentation) with a balance of hardware, system architecture and application software expertise
Proven track record in CPU and server system architecture, server benchmarks, GPU computing, FPGA accelerators, and server platform enablement
Excellent problem-solving, time-management, prioritization, and organizational skills, able to lead complex problems, involving multi-disciplined, multi-functional teams and many priorities at once
Ability to cultivate strong internal (sales, marketing, engineering) and external (customer) relationships
Physical requirement: able to lift up to 50 lbs. (racking hardware)
Willing to travel up to 25%
Proven experience as a senior level engineer (or equivalent technical role) balanced with experience in a customer-facing role
Proven experience in server platform architecture and/or platform development experience
Proven knowledge in any of these market verticals: cloud computing / benchmarking, high performance computing, networking, software defined storage and data analytics
Expertise in server software ecosystem in the one or more of these areas: Windows Server, Linux, hypervisors (Linux-KVM and Xen), NGINX, Redis, Apache Web Server, existing cloud offering such as AWS EC2, GCP and Microsoft Azure, and profiling / performance optimization tools

Job Responsibility

Articulate the benefits of AMD based technology offerings for the cloud service provider and MDC market verticals
Provide hands-on, expert-level technical guidance to systems engineers and application developers
Partner with other AMD subject matter authorities to tackle specific customer challenges
Lead technical design sessions
architect and detail technical solutions that are aligned with end-user objectives
Architect, install and test solutions in-house, as needed, to ensure successful deployments and evaluations
Design and lead the execution of evaluations to ensure a quality solution is delivered, providing technical assistance to sales for overall account strategy based on AMD datacenter solutions
Gather a solid understanding of the competitive landscape and clearly articulate the technical differentiation and value proposition associated with AMD versus our competitors
Drive customer feedback into AMD sales, business unit and engineering teams
Provide technical guidance to sales personnel and the customer in the evaluation, design and development of AMD based server and/or data center solutions as identified by sales leadership

Fulltime

New

Teradata Infrastructure Dba

Role: Teradata Infrastructure DBA. Location: Seattle, WA/ Dallas TX (Day 1 onsit...

Location

United States , Seattle, WA; Dallas, TX

Salary:

160000.00 USD / Year

Realign

Expiration Date

Until further notice

Requirements

Teradata platform expertise
Deep knowledge of Teradata architecture: parsing, BYNET, AMP, vproc, fallback, hashing, PDCR, fallback, and spool management
Data distribution and primary index design
collecting statistics and understanding optimizer behavior
Experience with recent Teradata versions and releases migration/upgrade planning: TD 16.XX, TD 17.XX and preferably TD 20.XX
System administration
Provisioning and managing Teradata nodes and clusters (physical and virtual)
OS-level skills: Linux administration (SLES/RHEL/CentOS/Oracle Linux) for Teradata on Linux, including kernel tuning, package management, user and permissions management
Storage subsystem knowledge: SAN, NAS, Fibre Channel, LUNs, RAID, and how storage impacts Teradata I/O and spool
Performance tuning and troubleshooting

Job Responsibility

Installs, configures and upgrades Teradata software and related products
Backup, restore, migrate Teradata data and objects
Establish and maintain backup and recovery policies and procedures
Manages and monitor system performance. proactively monitor the database systems to ensure secure services with minimum downtime
Implements and maintains database security
Sets up and maintains documentation and standards
Supports multiple Teradata Systems including independent marts/ enterprise warehouse
Work with the team to ensure that the associated hardware resources allocated to the databases and to ensure high availability and optimum performance
Responsible for improvement and maintenance of the databases to include rollout and upgrades
Responsible for implementation and release of database changes as submitted by the development team, Working with end customer

Fulltime

New

National Resident RN

As our National Resident RN, you will experience a dynamic and supportive reside...

Location

United States , Silverdale

Salary:

47.88 - 80.88 USD / Hour

American Nursing Care

Expiration Date

Until further notice

Requirements

Graduation from an accredited school of nursing upon hire and one to two years Med/Surg experience with completion of Mother/Baby Education program or, New graduate with completion of senior practicum in L&D, Mother/Baby unit or nursery
Registered Nurse: WA, upon hire
Current American Heart Association Healthcare Provider BLS certification
Neonatal Resuscitation Program, within 6 months of date of hire

Job Responsibility

Deliver individualized patient care by collaborating with physicians and multidisciplinary teams, administering treatments, monitoring vital signs, and educating patients and families
Actively engage in our comprehensive, evidence-based Residency Program, utilizing clinical orientation, practice, and mentorship
Demonstrate a passion for learning and teamwork within a collaborative, patient-centered environment
Evidence-based Practice (EBP) and Patient Care: Builds skills to utilize current evidence based practice knowledge, the nursing process, critical thinking and problem solving skills to provide holistic care to individuals across the lifespan and care continuum
Interprofessional Collaboration and Communication: Learns to collaborate and communicate with the interprofessional team to ensure effective and efficient patient care delivery and the achievement of desired patient outcomes
Leadership: Develops accountability for own practice, delegated care, and the coordination of care delivery
Professionalism: Acquires and maintains knowledge in nursing practice and assumes responsibility for the professional development of self
Attainment of Core Competencies: Taking Ownership
Teamwork
Patient / Customer Focus

What we offer

health/dental/vision, FSA, matching retirement plans, paid vacation, adoption assistance, annual bonus eligibility, tuition assistance, retirement plan benefit(s) including, but not limited to, 401(k), 403(b), and other defined benefits offerings

Fulltime

Physical Design Lead - CPU Team

AMD

Location:
India , Bangalore

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
March 25, 2026

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