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Physical Design team within Cisco Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.
Job Responsibility:
Provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle
Responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning
Requirements:
A VLSI Design with extensive experience in backend design
B.Sc./M.Sc. in Electrical Engineering
Strong understanding of Place & Route flow
10+ years of hands-on experience in a relevant domain
4+ years of proven Management or Technical Leadership experience
Nice to have:
Deep understanding of all aspects of Physical construction and Integration
Knowledge in Physical Design Verification methodology LVS/DRC
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)