Physical Design Engineer Job at Duo Security (Yerevan)

Physical Design Engineer

Duo Security

Location:
Armenia , Yerevan

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Not provided

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Job Description:

This is a hybrid role with four days per week at Cisco’s Yerevan office. Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond. Working hand-in-hand with Front-End teams, we transform cutting-edge designs into industry-leading silicon solutions. Here, you'll have the opportunity to shape tomorrow's technology, driving advancements in power, performance, and reliability with every project. Together, we're building the foundation for the future of connectivity.

Job Responsibility:

Drive macro level RTL to gds implementation and signoff
Work with Front-End teams to understand the design architecture to ensure optimal physical implementation
Execute critical physical design tasks, including gate-level netlist synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing
Optimize designs to achieve industry-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification
Conduct Static Timing Analysis (STA), physical verification, formal verification and signoff closure to ensure high-quality results
Analyze and resolve Electromigration (EM) and IR-drop (IR) issues, meeting stringent signoff requirements for reliability and performance

Requirements:

Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field
6+ year minimum of hands-on experience in ASIC design and verification
Proven expertise in ASIC physical design and verification with a strong track record of delivering complex projects
Advanced knowledge of block-level synthesis, place-and-route (PnR), and timing closure
First-hand experience with industry-standard PnR and signoff tools such as Synopsys and Cadence

Nice to have:

Comprehensive understanding of all aspects of physical design construction, integration, and methodologies
Proficiency in Physical Design Verification, including techniques like LVS and DRC
Experience with physical design EDA tools and workflows
Advanced expertise in Static Timing Analysis (STA), timing closure, and design constraints
Proficiency in scripting languages like Tcl, Python, or Perl, with a focus on automation and efficiency improvements

Additional Information:

Job Posted:
January 19, 2026

Work Type:

Hybrid work

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