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WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: A senior technical contributor that drives end-to-end delivery of SOC solution and coordinates implementation and optimization across multiple teams. The position will involve interfacing with SOC Architecture, CAD and customer to plan, develop and optimize SOC design and implementation. This is an exciting opportunity to work on the cutting edge of APU or ASIC design. THE PERSON: You are a subject matter expert and strong technical contributor with SOC implementation experience. You excel as part of a team where communication and team skills are highly valued. KEY RESPONSIBILITIES: Technical lead on challenge PPA optimization and 3DIC solution Develop AI methods to implement FEINT and PD work efficiency improvement PREFERRED EXPERIENCE: Familiar with whole process of RTL-to-GDS Knowledge of advanced process nodes, like 2nm and 3nm Good knowledge for 3DIC design Experience of PPA optimization for high performance or low power design Experience advocating for technical solutions in a collaborative team environment, especially combining AI methods Excellent communication and collaboration skills ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in related discipline preferred LOCATION: Zhangdong Road, Shanghai
Job Responsibility
Technical lead on challenge PPA optimization and 3DIC solution
Develop AI methods to implement FEINT and PD work efficiency improvement
Requirements
Familiar with whole process of RTL-to-GDS
Knowledge of advanced process nodes, like 2nm and 3nm
Good knowledge for 3DIC design
Experience of PPA optimization for high performance or low power design
Experience advocating for technical solutions in a collaborative team environment, especially combining AI methods