Physical Design Engineer Job at AMD (Shanghai)

Physical Design Engineer

We are looking for an adaptive, self-motivative design verification engineer to ...

Location

China , Beijing

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering
Good at C/C++
Familiarity with SystemVerilog and modern verification libraries like UVM

Job Responsibility

Develop/Maintain tests for functional verification and performance verification at the core level
Build testbench components to support the next generation IP
Maintain or improve current test libraries to support IP level testing
Create hardware emulation build to verify the IP functional performance
Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility
Provide technical support to other teams

Physical Design Engineer

Experience in complete PNR from the floorplan, Placement, post-placement timing ...

Location

India , Bengaluru

Salary:

Not provided

DPIIND

Expiration Date

Until further notice

Requirements

Experience in complete PNR from the floorplan, Placement, post-placement timing closure, clock tree synthesis, Routing, Post route timing fixing, DRC fixing, PI fixing (IR violation), and closing all required matrices in ECO
Good knowledge of TCL, shell, and PERL scripting
Experience in APR (PNR) and ECO using ICC2 (Synopsys) & INNOVUS (cadence) Tools
Experience in working in 4nm,5 nm, 7nm, 10nm, and 16nm technology
Experience in doing floorplan with complex design and a large number of macros
Flow setup of synthesis, which includes the Timing constraints and logical, physical constraints
Experience: 5-10 Years

Fulltime

Physical Design Engineer

This individual contributor role sits within our physical design team and is cen...

Location

United States , San Francisco

Salary:

266000.00 - 445000.00 USD / Year

OpenAI

Expiration Date

Until further notice

Requirements

BS w/ 4+ or MS with 2+ or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
Demonstrated success in taping out complex silicon designs
Hands-on experience with block physical implementation and PPA convergence
Strong coding experience with python, bazel, TCL
Strong experience building physical design tools, flows and methodologies
Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure
Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation

Job Responsibility

Develop, build and own tools, flows and methodologies for physical implementation
Own physical implementation of floorplan blocks from floorplanning to final signoff
Collaborate with RTL designers to drive optimal block implementation solutions
Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners

What we offer

Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
401(k) retirement plan with employer match
Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
Mental health and wellness support
Employer-paid basic life and disability coverage
Annual learning and development stipend to fuel your professional growth
Daily meals in our offices, and meal delivery credits as eligible

Fulltime

Physical Design Engineer

Etched is looking for exceptional Physical Design engineers to join our team. In...

Location

United States , San Jose

Salary:

150000.00 - 275000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

5-10+ years of previous experience with PD
Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
Experience with back-end design and timing closure on advanced process nodes (5nm and below)
Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows
Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
Deeply creative and able to think from first principles

Job Responsibility

Deeply understand what is involved in physical design
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD infrastructure
Collaborate with RTL Designers and provide Physical Design feedback to improve PPA
Drive dashboards that show the convergence of projects related to PD
Optimize tool flows, working with EDA vendors to incorporate the latest features
Accountable for block level closure
Supervise the outsourcing of physical design to a 3rd party service

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office
Plus Significant Equity

Fulltime

Physical Design Engineer

In this role, you will be responsible for the implementation and signoff of comp...

Location

China , Beijing

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Full chip floorplan experience
Scripting language experience: Perl, Tcl, Python
Exposure to leadership or mentorship is an asset
Experience with high-performance CPU/GPU/AI accelerator physical design in advanced nodes (7nm and below)
Hands-on experience with low-power design techniques (power gating, multi-voltage, DVFS) and UPF/CPF flow
Familiarity with 3D-IC or chiplet-based design methodologies and associated tool flows
Knowledge of package-aware floorplanning and system-level co-design considerations
Experience with machine learning applications in physical design (e.g., auto-placement, routing prediction)
Prior exposure to design for testability (DFT) integration and post-silicon debug support
Proven track record of successful tape-outs in high-complexity SoC projects

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features
RTL-to-GDSII Implementation – Execute full physical design flow including synthesis, floorplanning, placement, CTS, routing, and signoff
Timing & Power Closure – Perform static timing analysis (STA), power analysis, and optimize designs to meet timing, power, and area goals
Physical Verification – Run DRC, LVS, and other verification checks to ensure design manufacturability
Methodology & Automation – Develop and maintain scripts to improve design efficiency and quality
Cross-functional Collaboration – Work with frontend, DFT, and CAD teams to resolve design issues and implement methodology improvements
Documentation & Reporting – Create clear documentation and regularly report progress to project stakeholders

Physical Design Engineer

This role has been designed as ‘Hybrid’ with an expectation that you will work o...

Location

India , Bangalore

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

4+ years experience in ASIC physical design
Experience with block implementation, extraction, timing and or full-chip designs
Strong communication skills
Strong hands-on TCL/Perl development skills
Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project
Track record of taping out complex chips on advanced process nodes

Job Responsibility

Responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation
Work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow
Experienced in design automation
Understanding of Timing constraints, SI prevention, Power reduction

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Staff Silicon Design Engineer (Physical Design)

We are looking for an adaptive, self-motivative Back End Physical Design enginee...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

9 years professional experience in the semiconductor industry
Experience in FinFET & Dual Patterning nodes such as 16/14/12 and sub-10nm nodes
High-frequency design experience
Excellent physical design and timing background
Synopsys Tools Experience Not a Must But Preferred
MNC experience is a plus
Familiarity with all Design areas and tools and solid understanding of design/technology interactions
Good understanding of computer organization/architecture
Strong analytical/problem solving skills and pronounced attention to details
Must be a self-starter, and able to independently drive tasks to completion

Job Responsibility

Involves in Floorplan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
Experience in handling different PNR tools - Synopsys Design Compiler, ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
Involvement in not only Physical design, but also STA & timing closure, authoring methodology scripts in Tcl, Perl and/or Python
Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python
Hands on experience on 16nm, 14nm, 12nm, and sub-10nm projects

Fulltime

New

Sr Physical Design Engineer

This is an on-site, hybrid opportunity. This is not a remote work opportunity. E...

Location

United States , Austin

Salary:

162000.00 - 243000.00 USD / Year

Ericsson

Expiration Date

Until further notice

Requirements

10+ years of physical design experience and minimum of a BS EE/CE
Expert in one or many of these areas – Methods to improve PPA, RTL checks and Synthesis, STA Constraints, DFT clocking architecture, Physical design of high speed interface IPs
Knowledge of System Verilog or VHDL
Accomplished at problem resolution and execution per project plan/needs
Prior experience in a Senior or Lead Engineer role, including direct responsibility for guiding and mentoring junior team members and setting technical direction
Highly team oriented

Job Responsibility

Be an empowered designer tasked with improving PPA of Ericsson ASICs
Evaluate feasibility of architectural features through back end implementation
Partner with front end design teams to address timing, power and congestion challenges
Deliver a synthesized netlist to ASIC BE vendor, and collaborate with vendor to address physical design tradeoffs
Work with DFT and architecture teams to develop timing constraints
Provide technical leadership and direction for junior members of the team
Participate in defining flows, methods and drive continuous improvement

What we offer

Annual bonus
Choice of three medical plan options and a dental plan option
401(k) Plan with automatic 3% company contribution and matching
Basic life insurance and basic accidental death and dismemberment coverage
Short-term and long-term disability coverage
Stock Purchase Plan
15 days of accrued vacation per year
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time

Fulltime

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