CrawlJobs Logo

Physical Design Engineer

openai.com Logo

OpenAI

Location Icon

Location:
United States , San Francisco

Category Icon
Category:
IT - Software Development

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

266000.00 - 445000.00 USD / Year
Save Job
Save Icon
Apply Position

Job Description:

This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators. You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality.

Job Responsibility:

  • Develop, build and own tools, flows and methodologies for physical implementation
  • Own physical implementation of floorplan blocks from floorplanning to final signoff
  • Collaborate with RTL designers to drive optimal block implementation solutions
  • Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners

Requirements:

  • BS w/ 4+ or MS with 2+ or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
  • Demonstrated success in taping out complex silicon designs
  • Hands-on experience with block physical implementation and PPA convergence
  • Strong coding experience with python, bazel, TCL
  • Strong experience building physical design tools, flows and methodologies
  • Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure
  • Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation

Nice to have:

  • Experience with AI or HPC-focused chips
  • Experience with optimizing PPA for high performance compute cores
  • Hands-on experience with top-level design methodologies
What we offer:
  • Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
  • Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
  • 401(k) retirement plan with employer match
  • Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
  • Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
  • 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
  • Mental health and wellness support
  • Employer-paid basic life and disability coverage
  • Annual learning and development stipend to fuel your professional growth
  • Daily meals in our offices, and meal delivery credits as eligible
  • Relocation support for eligible employees
  • Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided
  • Offers Equity
  • Performance-related bonus(es) for eligible employees

Additional Information:

Job Posted:
February 21, 2026

Employment Type:
Fulltime
Work Type:
On-site work
Icon
OpenAI - All Job Offers
Job Link Share:
Copy Link Icon
Facebook Icon Twitter Icon LinkedIn Icon

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for Physical Design Engineer

Asic Physical Design Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...
Location
Location
United States , San Jose
Salary
Salary:
148000.00 - 340500.00 USD / Year
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BS degree in electrical engineering
  • computer engineering
  • or a related field with 7+ years of experience in block or full-chip physical design
  • Deep design experience in large SoC designs
  • including IP integration
  • padring design
  • bump planning
  • and RDL routing strategy
  • Extensive knowledge and practices in Physical Design
  • including physically aware synthesis
Job Responsibility
Job Responsibility
  • Implement physical design at the large SoC chip level from RTL to GDSII
  • create a design database ready for manufacturing
  • Interact with IP vendors to understand IP integration requirements and integrate all blocks
  • IPs
  • and sub-chips at a large SoC level
  • Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement
  • Build full chip floorplan
  • including pads/ports/bump placement
  • block placement and optimization
  • block pins placement and alignment
What we offer
What we offer
  • Comprehensive suite of benefits that supports physical
  • financial and emotional wellbeing
  • Personal and professional development programs
  • Unconditional inclusion and flexibility to manage work and personal needs
  • Fulltime
Read More
Arrow Right

Physical Design Engineer

This role has been designed as ‘Hybrid’ with an expectation that you will work o...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 4+ years experience in ASIC physical design
  • Experience with block implementation, extraction, timing and or full-chip designs
  • Strong communication skills
  • Strong hands-on TCL/Perl development skills
  • Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project
  • Track record of taping out complex chips on advanced process nodes
Job Responsibility
Job Responsibility
  • Responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation
  • Work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow
  • Experienced in design automation
  • Understanding of Timing constraints, SI prevention, Power reduction
What we offer
What we offer
  • Health & Wellbeing
  • Personal & Professional Development
  • Unconditional Inclusion
  • Fulltime
Read More
Arrow Right

Senior Physical Design Engineer

As a Senior Physical Design Engineer, you will be responsible for the physical i...
Location
Location
United States , Batavia, Illinois
Salary
Salary:
Not provided
nhanced-semi.com Logo
NHanced Semiconductors
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • US Citizenship
  • 5+ years of experience in physical design, specifically in ASIC, SoC, or advanced packaging (2.5D, 3DIC) technologies
  • Hands-on experience with Git-based version control systems for managing design revisions
  • Experience with timing closure and signal integrity
  • Proficiency in Cadence tools for physical design, timing analysis, and signoff
  • Strong understanding of RTL-to-GDSII flows, including floorplanning, power planning, place-and-route, and timing closure
  • Working knowledge of parasitic extraction (PEX), power integrity (PI), and thermal analysis in multi-die environments
  • Ability to work independently with minimal supervision and drive tasks to completion
  • Excellent verbal and written communication skills for collaboration across engineering teams
  • Strong debugging skills and ability to analyze tool reports, logs, and simulation results
Job Responsibility
Job Responsibility
  • Drive full-chip physical implementation of 2.5D interposer and ASIC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
  • Ensure design compliance with timing, power, and area (PPA) requirements, as well as DFM, DRC, and LVS constraints
  • Utilize Cadence tools (Innovus, Virtuoso, Tempus, Voltus, Pegasus, etc.) for physical design, verification, and signoff
  • Develop and execute timing closure strategies, working with STA engineers to meet performance goals
  • Optimize power distribution networks (PDN) and electromigration (EM) reliability in multi-die packaging environments
  • Work with package and system engineers to optimize die-to-die interconnect, bump placement, and TSV integration
  • Collaborate with RTL designers, DFT engineers, and backend teams to ensure seamless integration
  • Implement ECOs (Engineering Change Orders) and efficiently iterate design revisions
  • Utilize Git-based version control workflows for design database management and collaborative development
  • Identify and resolve congestion, signal integrity (SI), and crosstalk issues in complex designs
Read More
Arrow Right

Senior SoC/ASIC Physical Design Engineer

As a Senior SoC/ASIC Physical Design Engineer, you will work on developing and i...
Location
Location
United States , Irvine
Salary
Salary:
Not provided
xcelerium.com Logo
Xcelerium
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 5+ years of ASIC and/or physical design flow development experience
  • Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools)
  • Scripting experience with Python, Tcl, or Perl
  • Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation
  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
  • Strong experience with Synopsys EDA tools including understanding of their capabilities and underlying algorithms
  • Strong knowledge of deep sub-micron FinFET and CMOS solid state physics
  • Strong knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
  • Deep understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
  • Familiar with CMOS analog circuit and physical design
Job Responsibility
Job Responsibility
  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
  • Fulltime
Read More
Arrow Right

Microprocessor VLSI Physical Design Engineer

At AMD, our mission is to build great products that accelerate next-generation c...
Location
Location
United States , Fort Collins
Salary
Salary:
139360.00 - 209040.00 USD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BS/MS in EE, CS, CSE (or similar), plus 8+ years hardware design experience
  • Hands-on experience in high-speed VLSI design
  • Excellent understanding of computer architecture, hardware concepts & design tradeoffs required
  • Knowledge of Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, electromigration, Physical Verification and Sign Off
  • Comprehend complex Verilog RTL and make minor modifications for timing or power
  • Knowledge of digital circuits, high speed flops, synchronizers, level shifters, and SRAM
  • Familiar with programing languages such as Perl, C, tcl, etc.
Job Responsibility
Job Responsibility
  • Technical lead for high-speed VLSI design in deep sub-micron processes
  • Work closely with RTL and physical designers across multiple sites to optimize power, performance, area, and schedule
  • Solve design and tool problems requiring ground-breaking approaches and champion innovation across the organization
  • Create technical presentations for peers and management
  • Guide and mentor junior engineers.
  • Fulltime
Read More
Arrow Right

Senior Physical Design Engineer

We are looking for an adaptive, self-motivative physical design engineer to join...
Location
Location
Malaysia , Penang
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • MSEE with 2+ years or Bachelor with 5+ years of industrial experience in ASIC design
  • Familiar with Back-End (physical design) EDA tools
  • Hands on experience in large scale ASIC chip physical design
  • Knowledgeable in all aspects of deep submicron ASIC design flow
  • Successfully gone through several complete product development cycles
  • Demonstrate strong problem-solving and work well with cross-functional teams
  • Good listening, writing and speaking English
  • Good communication skills, strong interpersonal skills and flexibility
  • Dedicated, hardworking and good team player
  • Familiar with Unix/Linux environment and good at scripts
Job Responsibility
Job Responsibility
  • Drive and improve AMD's abilities to deliver the MI/Navi series of GPU products to market
Read More
Arrow Right

Hardware Design Engineering Intern/Co-op

We are seeking a highly motivated Hardware Design engineering intern/co-op to jo...
Location
Location
Canada , Markham
Salary
Salary:
65000.00 CAD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Currently enrolled in a Canada based University into a Bachelor's degree program majoring in Electrical engineering or Computer engineering or a related field
  • Strong semiconductor device physics knowledge
  • Digital /Logic circuits and VLSI
  • Verilog or VHDL hardware description languages
  • Exposure to UVM methodologies
  • Scripting languages (e.g. Python, Perl, TCL, Ruby), Shell / UNIX scripting, C/C++, MATLAB
  • Interest or experience in Machine Learning
  • ASIC design
  • Knowledge of Ruby on Rails and MySQL
  • Linux/Unix environment
Job Responsibility
Job Responsibility
  • Collaborate with Design Engineers on the physical design verification and physical implementation for some of our ASIC
  • Work on Memory interface simulation work eg. GDDR7, HBM, UCIE
  • Work on Discreate and Embedded hardware products and chip to chip interconnect
  • Actively participate in RTL design in Verilog
  • Synthesis with timing driven placement and design for power (DFP)
  • Floor planning, Power distribution, Clock distribution, Block/Chip Place & Route, EM/IR analysis, Timing closure, Static Timing Analysis
  • Analysis of logical equivalent check, RTL clocking analysis, static power analysis, and design for test (DFT)
  • Build test libraries and models by using advanced verification languages such as System Verilog, UVM and C++
  • Fulltime
Read More
Arrow Right

Electrical Design Engineer

The Electrical Design Engineer (LV/MV) will design and develop protection and co...
Location
Location
United Kingdom , Colchester
Salary
Salary:
35000.00 - 50000.00 GBP / Year
hederahiring.com Logo
Hedera Hiring Ltd
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • A minimum of HNC/HND/Degree or equivalent in Electrical/Electronic Engineering or Physics
  • Incorporated Engineer/member of the IET/Chartered Engineer
  • Experience in design and planning of DNO/IDNO network for 11kV 33kV and 66kV or higher
Job Responsibility
Job Responsibility
  • Design and develop protection and control schemes for LV/MV and EHV substations
  • Produce and maintain accurate main connection and protection drawings
  • Calculate protection settings
  • Perform cable calculations for voltages up to 66 kV
  • Provide design expertise for substations at various voltage levels
  • Conduct and analyse power system studies such as load flow and short-circuit studies
  • Ensure all designs comply with relevant regulations and standards
Read More
Arrow Right
Jobs by Category
Art and Entertainment Jobs Banking Jobs Call Center Jobs Construction Jobs Consulting Jobs Customer Service Jobs Education Jobs Energy Jobs Finance Jobs Gastronomy Jobs Health and Beauty Jobs Hospitality and Tourism Jobs Human Resources Jobs Insurance Jobs IT - Administration Jobs IT - Software Development Jobs Legal Jobs Logistics Jobs Manufacturing Jobs Marketing, Digital Marketing, SEO, SEM Jobs Media Jobs Nursing Jobs Office Administration Jobs Pharmacy Jobs Physical Work Jobs Public Relations Jobs Public Sector Jobs Purchasing Jobs Quality Control Jobs Real Estate Jobs Research and Development Jobs Sales Jobs
Job Positions Jobs by Country
United States Jobs United Kingdom Jobs India Jobs Canada Jobs Australia Jobs Germany Jobs Ireland Jobs Poland Jobs
Company
Blog About Us Contact
Follow Us
Facebook
X (Twitter)
LinkedIn
Instagram
CrawlJobs Group
ITFlashcards AllDevBlogs
© 2026 CrawlJobs Ltd. All Rights Reserved
Terms & Conditions Privacy Policy