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We are seeking a seasoned Physical Design Lead with expertise or significant interest in handling complete Physical Design for a complex Chiplet. You have had significant success driving Full Chip Floorplan based on architecture, Defining Timing targets across PVT's, drive for Full Chip PnR and Tile PnR closure and monitor Signoff functions like Physical Verification, IREM etc., You are meticulous about Power, Performance and Area while keeping schedule in tact. This role also stretch you as a overall PD lead to work with IP teams, Architecture, Package and CAD/Methodology teams.
Job Responsibility
Own the Physical Design for one complete Chiplet on advanced technology nodes preferably TSMC 2nm or 3nm
Work with all external stakeholders like Architects, IP teams, CAD/Methodology teams and all internal PD stakeholders like FCFP, FCT, TilePnR, PV from technical standpoint
Drive for best PPA attainments, optimize latency on datapaths, work with package teams on power delivery and other interdependencies
Signoff the Chiplet for Tapeout from Physical Design aspect
Requirements
15+ years of experience in Physical Design handling full chip activities and signoff
Excellent communication, management, and presentation skills
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
Bachelor's or Master's degree in related discipline preferred