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The HW Interface Engineer serves as the engineering authority within the Solution Engineering Group, mentoring internal field teams, conducting critical HW Interface design reviews, and ensuring technical consistency across vendor-developed solutions. This role ensures that schematic, layout, and simulation reviews are conducted with rigor and consistency, particularly for strategic projects in high growth market such as High Power Computing and AI with technical governance and standardization.
Job Responsibility:
Lead and facilitate schematic, layout, and mechanical design reviews for vendor-developed hardware interfaces
Validate simulation results and ensure signal integrity, mechanical constraints, and manufacturability are addressed
Compare vendor capabilities to guide onboarding, project allocation, and quarterly reviews
Define and maintain technical standards for DIB design, including layout rules, signal routing, and mechanical part usage
Create and manage shared templates and documentation frameworks to ensure consistency across vendors
Mentor field engineers and internal stakeholders on best practices for reviewing vendor designs
Act as the technical reference for high-impact projects requiring elevated scrutiny and rapid turnaround
Contribute to the DIB technology roadmap and innovation initiatives
Requirements:
BSEE or equivalent required
MSEE preferred (EM/high speed a plus)
8–12+ years in high speed PCB/DIB design, SI/PI
IPC CID/CID+ and/or major EDA SI/PI certifications are a plus
Knowledge of Teradyne UltraFLEX test equipment is a plus
High-speed SI/PI expertise for complex DIB/load-boards: stack-ups, loss/crosstalk budgets, return-path control, via strategy, PDN target-Z, decoupling
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