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AMD Logo AMD · IT - Administration

Packaging Engineer

Taiwan, Hsinchu · Job Posted June 10, 2026
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Job Description

Candidate is required to work closely with oSATs and cross-functional teams to bring up and sustain for InFO, EFB/CoWoS-L,CoWoS-S, WLFO, FCBGA, LGA and chiplet packages.

Job Responsibility

  • Responsible for InFO, WFB/CoWoS-L, CoWoS, WLFO, FCBGA, LGA and Chiplet package Manufacturing readiness for New Product bring up at manufacturing site
  • Responsible for packaging yield, quality, cost and operation productivity improvements and sustaining activities
  • Drive assembly process baseline standardization and continuous improvement
  • Responsible for the packaging interaction activities among assembly, bump, 3D IC, HBM and wafer fab, wafer sort, Functional Test and Mark/Pack
  • Drive Assembly manufacturer to enhance process, equipment & material capability for future generation/technology products
  • Co-work with Packaging BU on NPI and Ramp Up readiness at manufacturing site
  • Proactively follow up task assignments and report status timely to stakeholders
  • Responsible to manage performance of assembly manufacturing site/supplier regarding yield & quality, out of control lot disposition, and any outliers with close loop on reporting
  • The role will require working together with both internal engineering counterparts & extensive interactions within the Package engineering organization, and interacting with several other internal organizations (procurement, supply chain, reliability, etc.) on program deliverables with accurate and timely reporting of program status with executive summary update throughout its life cycle
  • Responsible for strategic supplier management
  • Plan and execute change management from internal or external parties
  • Assist in additional duties as deemed fit by supervisor
  • Job may include other duties as assigned/ deemed fit by supervisor

Requirements

  • Min 8 years' experience in InFO or 2.5D/3D Bump/TSV/Packaging, Flip Chip BGA/LGA or WLFO process engineering with min total 7 years assembly work experience
  • Possess InFO, Chiplet packaging, 2.5D/3D TSV/Packaging, Flip Chip BGA/LGA process knowledge and Chip-Packaging Interaction knowledge
  • Lead and manage team experience
  • Strategic supplier management experience
  • Familiar with DOE and JMP
  • MS degree in Mechanical or Material or Chemical Engineering
  • Creative, highly motivated self-driven individual team player with the demonstrated ability to independently complete complex engineering tasks on/ahead of time/Lead & Drive for solutions and an aptitude to thrive in a fast-paced multi-tasking environment
  • Experience is Preparing reports /Presentation and ability to communicate Root cause and Resolution effectively
  • Creative, self-driven, highly motivated individual with demonstrated ability to independently manage complex engineering tasks
  • Strong interpersonal communication, analytical, project management, task & time management, and with excellent communication skills
  • Experience in managing horizontally across multiple internal functional organization
  • Experience in semiconductor engineering environment, with NPI to HVM experience
  • Fluent in both spoken and written English
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